Senior PnR Lead - High-Speed ASIC Digital Implementation

Octopyd; Sunnyvale (CA); Presencial; USD 180.000 - 260.000; Tempo integral

Resumo da vaga

Avicena is seeking a Physical Design (PnR) Lead in Sunnyvale, CA to own the digital implementation of our mixed-signal ASIC from synthesis through signoff. You will coordinate top-level floorplanning, clocking, and ECOs, while integrating dense repeated lane arrays and analog macros.

The role requires 10+ years in ASIC physical design, strong scripting with Tcl and Python, and hands-on experience with Cadence Innovus/Genus and Synopsys Fusion tools.

Qualificações

• BS in Electrical or Computer Engineering; MS preferred.
• 10+ years of ASIC physical design experience with block or full-chip netlist-to-GDS ownership.
• Strong scripting in Tcl and Python; ability to build reproducible flows.
• Experience with FinFET, multi-patterning, and advanced-node rules.
• Experience integrating analog/mixed-signal macros into digital top level.

Responsabilidades

• Own the digital implementation flow from synthesis through signoff: floorplan, power planning, placement, clock tree synthesis, routing and ECOs.
• Define and maintain timing constraints and drive tight timing closure across multiple corners.
• Plan top-level floorplan with analog leads; integrate analog macros and replicated lane arrays.
• Run early feasibility studies to surface issues before RTL freeze.
• Own implementation signoff: STA, IR drop, EM, crosstalk, physical verification and LEC.
• Define macro handoff checklist and coordinate with circuit owners to meet it.
• Build scripted, reusable flows and track quality across iterations.
• Hire and mentor PnR engineer; manage contract support during peak load.
• Coordinate with CAD/foundry on PDK and tool versions; work with packaging teams on bump/power plans.

Conhecimentos

Scripting (Tcl & Python)

Timing closure

ASIC physical design ownership

FinFET/multi-patterning awareness

Formação

BS in Electrical or Computer Engineering

Ferramentas

Cadence Innovus/Genus

Synopsys Fusion Compiler/ICC2

Tempus / PrimeTime

Voltus / RedHawk

Quantus / StarRC

Calibre / Pegasus

Descrição da vaga

Avicena is seeking a Physical Design (PnR) Lead in Sunnyvale, CA to own the digital implementation of our mixed-signal ASIC from synthesis through signoff. You will coordinate top-level floorplanning, clocking, and ECOs, while integrating dense repeated lane arrays and analog macros.

The role requires 10+ years in ASIC physical design, strong scripting with Tcl and Python, and hands-on experience with Cadence Innovus/Genus and Synopsys Fusion tools.