Physical Design (PnR) Lead

Octopyd; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Avicena is seeking a Physical Design (PnR) Lead in Sunnyvale, CA to own the digital implementation of our mixed-signal ASIC from synthesis through signoff. You will coordinate top-level floorplanning, clocking, and ECOs, while integrating dense repeated lane arrays and analog macros.

The role requires 10+ years in ASIC physical design, strong scripting with Tcl and Python, and hands-on experience with Cadence Innovus/Genus and Synopsys Fusion tools.

Qualifications

• BS in Electrical or Computer Engineering; MS preferred.
• 10+ years of ASIC physical design experience with block or full-chip netlist-to-GDS ownership.
• Strong scripting in Tcl and Python; ability to build reproducible flows.
• Experience with FinFET, multi-patterning, and advanced-node rules.
• Experience integrating analog/mixed-signal macros into digital top level.

Responsibilities

• Own the digital implementation flow from synthesis through signoff: floorplan, power planning, placement, clock tree synthesis, routing and ECOs.
• Define and maintain timing constraints and drive tight timing closure across multiple corners.
• Plan top-level floorplan with analog leads; integrate analog macros and replicated lane arrays.
• Run early feasibility studies to surface issues before RTL freeze.
• Own implementation signoff: STA, IR drop, EM, crosstalk, physical verification and LEC.
• Define macro handoff checklist and coordinate with circuit owners to meet it.
• Build scripted, reusable flows and track quality across iterations.
• Hire and mentor PnR engineer; manage contract support during peak load.
• Coordinate with CAD/foundry on PDK and tool versions; work with packaging teams on bump/power plans.

Skills

Scripting (Tcl & Python)

Timing closure

ASIC physical design ownership

FinFET/multi-patterning awareness

Education

BS in Electrical or Computer Engineering

Tools

Cadence Innovus/Genus

Synopsys Fusion Compiler/ICC2

Tempus / PrimeTime

Voltus / RedHawk

Quantus / StarRC

Calibre / Pegasus

Job description

Physical Design (PnR) Lead

Location: Sunnyvale, CA, US

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a Physical Design Lead to own digital implementation of our mixed-signal ASIC, from synthesis through signoff, and to integrate it with large custom analog macros and dense repeated lane arrays. You will set up the flow, own timing closure and signoff, and build a small implementation team as the program ramps.

Key Responsibilities

• Own the digital implementation flow from synthesis through signoff: floorplan, power planning, placement, clock tree synthesis, routing and ECOs.
• Define and maintain timing constraints with the digital team, and drive multi-mode, multi-corner timing closure including on-chip variation.
• Plan the top-level floorplan with the head of physical design and the analog leads; integrate custom analog macros and repeated arrays through agreed abstracts, timing models, pin and power interfaces.
• Run early feasibility studies (congestion, timing, power) with preliminary netlists and macro abstracts so problems surface before RTL freeze.
• Own implementation signoff: STA, IR drop and EM, crosstalk and signal integrity, physical verification and logical equivalence.
• Define the macro handoff checklist (abstracts, timing libraries, extracted views, pin and power rules) and work with circuit owners to meet it.
• Build scripted, reproducible flows and track quality of results and runtime across iterations.
• Hire, mentor and direct a PnR engineer, and manage contract support during peak load.
• Coordinate with CAD/foundry on PDK, tech files and tool versions, and with package/SI-PI on bump and power plans.

Qualifications

Required

• BS in Electrical or Computer Engineering (MS preferred) with 10+ years of ASIC physical design, including ownership of block or full-chip netlist‑to‑GDS for multiple tapeouts.
• Hands‑on expertise with Cadence Innovus/Genus or Synopsys Fusion Compiler/ICC2, and signoff tools such as Tempus or PrimeTime, Voltus or RedHawk, Quantus or StarRC, and Calibre or Pegasus.
• Strong command of timing constraints, MMMC, OCV/AOCV/POCV, clock tree strategies and ECO flows.
• FinFET implementation experience, including multi‑patterning and advanced-node design rules.
• Experience integrating hard analog/mixed‑signal macros into a digital top level.
• Strong Tcl and Python scripting.

Preferred

• Implementation of mixed‑signal chips with high‑speed I/O, SerDes or arrays of repeated lanes.
• Hierarchical implementation and top‑level assembly of large chips.
• Low‑power implementation with multiple voltage domains (UPF).
• Experience leading engineers and managing contractors.
• Direct work with foundries and packaging teams through tapeout.

Key Competencies

• Ownership: drives the chip to clean signoff, not just individual runs.
• Technical judgment: makes timing, area, power and schedule trade‑offs with data.
• Collaboration: works naturally across analog, digital and packaging teams.
• Methodical: builds flows others can reproduce and trust.