Physical Design Lead: Digital & Mixed-Signal PnR

Avicena Tech; Sunnyvale (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Avicena Tech seeks a Physical Design (PnR) Lead in Sunnyvale, CA to own the digital implementation of a mixed-signal ASIC and to integrate it with dense analog macros and lane arrays. You will set up the flow, own timing closure, and build a small implementation team as the program ramps.

Responsibilities include defining timing constraints, signoff (STA, IR drop, EM, SI), and coordinating with CAD/foundry partners. Strong scripting and leadership are essential.

Qualifications

• Requires 10+ years ASIC physical design experience.
• Experience owning block or full-chip netlist-to-GDS tapeouts.
• Strong Tcl and Python scripting.
• FinFET and advanced-node design rules experience.
• Experience integrating analog/mixed-signal macros into digital top level.

Responsibilities

• Own digital implementation flow from synthesis through signoff (floorplan, P&R, CTS, routing).
• Define timing constraints and drive multi-mode, multi-corner timing closure.
• Plan top-level floorplan with analog leads; integrate macros and repeated lanes.
• Run early feasibility studies (congestion, timing, power) before RTL freeze.
• Own implementation signoff: STA, IR drop, EM, crosstalk, SI/PI, and LVS/ELF checks.
• Define macro handoff checklists and ensure tool/DB consistency across teams.
• Build scripted, reproducible flows and lead a small PnR team; manage contractors.

Skills

ASIC physical design

Timing closure

Scripting (Tcl/Python)

Team leadership

Digital-Analog integration

Education

B.S. Electrical or Computer Engineering

M.S. preferred

Tools

Cadence Innovus

Genus

Synopsys Fusion Compiler

ICC2

Tempus

PrimeTime

Voltus

RedHawk

Quantus

StarRC

Calibre

Pegasus

Job description

Avicena Tech seeks a Physical Design (PnR) Lead in Sunnyvale, CA to own the digital implementation of a mixed-signal ASIC and to integrate it with dense analog macros and lane arrays. You will set up the flow, own timing closure, and build a small implementation team as the program ramps.

Responsibilities include defining timing constraints, signoff (STA, IR drop, EM, SI), and coordinating with CAD/foundry partners. Strong scripting and leadership are essential.