Physical Design Engineer (PnR) for Mixed‑Signal ASICs

Octopyd; Sunnyvale (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Avicena is seeking a Physical Design Engineer (PnR) to implement and close digital blocks and top-level partitions of our mixed-signal ASIC. You will work with the PnR lead to take designs from netlist to clean signoff in Sunnyvale, CA.

Key tasks include synthesis, floorplanning, placement, CTS and routing; timing across modes; signoff checks (STA, IR drop, EM); integrating analog macros; scripting in Tcl/Python; and supporting tapeout.

Qualifications

• 3+ years of ASIC physical design experience.
• Hands-on experience with the listed CAD tools and STA.
• Familiar with FinFET implementation and signoff processes.

Responsibilities

• Run synthesis, floorplanning, placement, clock tree synthesis and routing for blocks and partitions.
• Close timing across modes and corners, and implement ECOs.
• Run signoff checks: STA, IR drop and EM, physical verification and logical equivalence.
• Integrate analog macros and repeated arrays following the macro handoff checklist.
• Maintain and improve implementation scripts.
• Support tapeout and post-tapeout ECOs.

Skills

Tcl scripting

Python scripting

FinFET implementation

Detail-oriented

Education

Bachelor's or MS in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

Tempus/PrimeTime

Calibre/Pegasus

Job description

Avicena is seeking a Physical Design Engineer (PnR) to implement and close digital blocks and top-level partitions of our mixed-signal ASIC. You will work with the PnR lead to take designs from netlist to clean signoff in Sunnyvale, CA.

Key tasks include synthesis, floorplanning, placement, CTS and routing; timing across modes; signoff checks (STA, IR drop, EM); integrating analog macros; scripting in Tcl/Python; and supporting tapeout.