Senior Engineer, PLL Design

Conductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Holidays and sick leave

401k and benefits

Fertility/adoption stipend

Medical/dental/vision

Job summary

Samsung Semiconductor Inc. seeks a Senior/Staff PLL Designer to create high‑performance PLLs and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O in 5nm–28nm CMOS technologies.

You will model, verify, and optimize PLLs; collaborate across digital, layout, and systems teams; support bring‑up and characterization of silicon in lab environments.

Qualifications

• Bachelor’s degree in related field; 5+ years experience for Senior or Master’s with 3+ years for Staff; PhD with 0 years is acceptable.
• Extensive hands‑on PLL design in deep sub‑micron CMOS (5nm-28nm).
• Strong knowledge of phase noise, jitter, loop dynamics and PLL architectures.

Responsibilities

• Design PLLs and clock generation circuits for RF/SerDes.
• Develop PLL blocks: VCO/DCO, charge pumps, loop filters, PDs, dividers, phase interpolators.
• Model system performance with Matlab/Simulink; perform Monte Carlo analysis.
• Silicon verification: transistor‑level sim, jitter budgeting, cadence/AMS flows.
• Collaborate with digital, layout, and systems teams to meet specs.

Skills

PLL Design

CMOS 5nm-28nm

VCO/DCO

Matlab/Simulink

Verilog/SystemVerilog

IC design CAD tools

RTL calibration concepts

Lab characterization

Digital calibration RTL

Problem solving & communication

Education

Bachelor's degree in related field

Master's degree in related field

PhD (0 years experience)

Tools

Spectre/SpectreRF

AMS simulator

Job description

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Samsung Semiconductor Inc is looking for a talented Senior/Staff PLL Designer with strong background and hands‑on experience in PLL and clock generation circuit design. The candidate will work on the design and development of high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O applications in advanced deep‑submicron CMOS technologies.

What You’ll Do

• Design PLLs and clock generation circuits (integer-N, fractional-N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications
• Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators
• Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink
• Drive design verification including transistor-level simulation, Monte Carlo analysis, and silicon correlation
• Collaborate with digital, layout, and systems teams to deliver PLL IPs meeting performance, power, and area targets
• Support bring-up, characterization, and debug of silicon prototypes in the lab

What You Bring

• Bachelor’s with 5+ years of experience or Master's with 3+ years of experiences or PhD with 0 years of experience in a related field.
• Extensive hands‑on experience designing PLLs in deep sub‑micron CMOS (5nm-28nm), including at least one of: integer-N, fractional-N, digital PLL, or sub‑sampling PLL topologies
• Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs
• Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator
• Strong Matlab/Simulink skills for behavioral modeling and system-level analysis
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation
• Solid understanding of layout-sensitive design and ability to guide critical PLL layout (LC tank, charge pump, reference path)
• Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment
• Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits, including frequency calibration, phase calibration, and background self‑calibration logic
• Excellent problem‑solving, analytical, and communication skills

What We Offer

• What We Offer The pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
• Give BackWith a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
• Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
• Care for FamilyWhatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
• Prioritize Emotional WellnessWith on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.
• Stay FitEating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
• Embrace FlexibilityBenefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.

Base Pay Range

$138,000 - $206,000 USD

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Our Commitment to Innovation and Fairness

At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision‑maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.

Applicant Privacy Policy https://semiconductor.samsung.com/about-us/careers/us/privacy/

The application deadline for this role is December 21, 2026