Senior PLL Design Architect for High-Speed Transceivers

Celero Communications, Inc.; San Jose (CA); Sur place; USD 150 000 - 250 000; Plein temps

Résumé du poste

Celero Communications, Inc. seeks a Principal PLL Design Engineer to lead high-speed clocking circuit development for next-generation optical transceivers and SerDes. You will architect and implement PLLs, analyze phase noise, and guide tape-out efforts.

You should have a Master’s or PhD in EE with 5+ years in PLL design, experience with 16nm–2nm nodes, Cadence Virtuoso, EMX/HFSS, and MATLAB. Excellent communication is essential, with a track record of production-level designs.

Qualifications

• Master’s degree or PhD in Electrical Engineering with 5+ years of PLL design experience.
• Experience with advanced node processes (16nm–2nm).
• Strong communication and documentation skills.

Responsabilités

• Evaluate PLL topologies (integer-N, fractional-N, ADPLL) to meet specs.
• Design and simulate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level.
• Address reliability issues in advanced nodes (self-heating, electromigration, VCO linearization).
• Review layouts to ensure floorplanning, matching, and parasitic minimization.
• Lead PLL bring-up and characterize performance in the lab.
• Perform system-level simulations for PLL integration into transceivers.

Connaissances

PLL design

Phase noise analysis

VCO design

LDOs

Communication skills

Formation

Master's or PhD in Electrical Engineering

Outils

Cadence Virtuoso

EMX/HFSS

MATLAB

Description du poste

Celero Communications, Inc. seeks a Principal PLL Design Engineer to lead high-speed clocking circuit development for next-generation optical transceivers and SerDes. You will architect and implement PLLs, analyze phase noise, and guide tape-out efforts.

You should have a Master’s or PhD in EE with 5+ years in PLL design, experience with 16nm–2nm nodes, Cadence Virtuoso, EMX/HFSS, and MATLAB. Excellent communication is essential, with a track record of production-level designs.