Senior Engineer, PLL Design

Samsung-Semiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

Charitable matching

4+ weeks PTO

Fertility/adoption stipend

Confidential therapy services

Onsite gym & cafe

Flexible work environment

Job summary

Samsung Semiconductor Inc. (SSI) seeks a Senior/Staff PLL Designer to craft PLLs and clocking subsystems for RF transceivers and SerDes in advanced CMOS tech.

You’ll model, verify, and characterize PLLs, collaborating with digital, layout and systems teams to hit performance, power and area goals. The role requires a Master’s with 2+ years or PhD with 0 years, strong Spectre/SpectreRF/AMS, Matlab/Simulink, and Verilog/SystemVerilog skills, plus lab phase-noise and jitter experience.

Qualifications

• Master’s degree with 2+ years of experience or PhD with 0 years of experience in a related field.
• Experience designing PLLs in deep sub-micron CMOS (5nm-28nm).
• Strong understanding of phase noise, jitter, loop dynamics and fractional spurs.
• Proficiency with IC design CAD tools (Spectre/SpectreRF/AMS).
• Proficient in Matlab/Simulink for modeling and analysis.
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation.
• Experience RTL design and digital calibration concepts.

Responsibilities

• Design PLLs and clock generation circuits for RF and SerDes applications.
• Develop and verify PLL building blocks: VCO/DCO, charge pumps, loop filters, PDs, dividers, and interpolators.
• Model, analyze, and budget jitter and phase noise.
• Collaborate with digital, layout and systems teams to meet performance/power/area targets.
• Support bring-up, characterization and silicon debug in the lab.

Skills

PLL design

CMOS design

Matlab/Simulink

Verilog/SystemVerilog

Lab characterization

RTL design

Layout guidance

Education

Master’s degree in related field

PhD in related field

Tools

Spectre

SpectreRF

AMS simulator

Job description

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day–including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

SSI is looking for a talented Senior/Staff PLL Designer with strong background and hands‑on experience in PLL and clock generation circuit design. The candidate will work on the design and development of high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O applications in advanced deep‑submicron CMOS technologies.

What You’ll Do

• Design PLLs and clock generation circuits (integer‑N, fractional‑N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications
• Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators
• Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink
• Drive design verification including transistor-level simulation, Monte Carlo analysis, and silicon correlation
• Collaborate with digital, layout, and systems teams to deliver PLL IPs meeting performance, power, and area targets
• Support bring‑up, characterization, and debug of silicon prototypes in the lab

What You Bring

• Master’s with 2+ years of experiences or PhD with 0 years of experience in a related field.
• Extensive hands‑on experience designing PLLs in deep sub-micron CMOS (5nm‑28nm), including at least one of: integer‑N, fractional‑N, digital PLL, or sub-sampling PLL topologies
• Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs
• Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator
• Strong Matlab/Simulink skills for behavioral modeling and system-level analysis
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation
• Solid understanding of layout-sensitive design and ability to guide critical PLL layout (LC tank, charge pump, reference path)
• Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment
• Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits, including frequency calibration, phase calibration, and background self-calibration logic
• Excellent problem-solving, analytical, and communication skills.

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job‑related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

• Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
• Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
• Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, caregiver support, and medical travel support.
• Prioritize Emotional Wellness With on‑demand apps and free confidential therapy sessions, you’ll have support no matter where you are.
• Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
• Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.

Base Pay Range

$138,000 - $206,000 USD

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Our Commitment to Innovation and Fairness

At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision‑maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.

We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.

At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.

By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

Applicant Privacy Policy

https://semiconductor.samsung.com/about-us/careers/us/privacy/

Voluntary Self‑Identification

For government reporting purposes, we ask candidates to respond to the below self‑identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Samsung Semiconductor’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability.

A "recently separated veteran" means any veteran during the three‑year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.

The application deadline for this role is January 3, 2027