Principal PLL Design Engineer - High-Speed Transceivers

Celero Communications, Inc.; United States; À distance; USD 180 000 - 260 000; Plein temps

Résumé du poste

Celero Communications, Inc. seeks a Principal PLL Design Engineer to architect and implement advanced PLLs for high-speed optical transceivers and SerDes systems.

You will lead design, simulation, and tape-out activities using Cadence Virtuoso in a fast-growing startup environment. Candidates should have 5+ years of PLL design experience, expertise in VCOs, phase noise, and layout verification, and be proficient with Cadence tools and MATLAB for system-level modeling.

Qualifications

• Master's degree and/or PhD in Electrical Engineering or related field.
• 5+ years of PLL design experience including tape-out experience.

Responsabilités

• Understand trade-offs between PLL topologies to meet power, area, jitter, and frequency specs.
• Architect, design and simulate analog/mixed-signal PLL blocks (VCOs, CPs, dividers, PFDs, loop filters).
• Supervise layouts for floorplanning, matching, and parasitic minimization.
• Lead PLL bring-up and characterize performance in lab; validate integration into transceivers.

Connaissances

PLL design experience

Phase noise analysis

VCO design

Cadence Virtuoso

MATLAB

Formation

Master's degree or PhD in Electrical Engineering

Outils

Cadence Virtuoso

EMX/HFSS

MATLAB

Description du poste

Celero Communications, Inc. seeks a Principal PLL Design Engineer to architect and implement advanced PLLs for high-speed optical transceivers and SerDes systems.

You will lead design, simulation, and tape-out activities using Cadence Virtuoso in a fast-growing startup environment. Candidates should have 5+ years of PLL design experience, expertise in VCOs, phase noise, and layout verification, and be proficient with Cadence tools and MATLAB for system-level modeling.