Senior SerDes Clocking Architect – Ultra-Low Jitter PLLs

Upscale, Inc.; Santa Clara (CA); On-site; USD 313,000 - 353,000; Full time

Job summary

Upscale, Inc. seeks a senior technical leader to define the clocking architecture for its next-generation SerDes platform. You will work across analog, mixed-signal, digital, layout and system teams to deliver exceptional timing performance in advanced CMOS at 5nm and below.

You will lead ultra-low-jitter PLL design, explore hybrid architectures, and drive silicon execution, verification, and correlation, with a focus on 100G+ per-lane SerDes clocking. This role is based in the Santa Clara area.

Qualifications

• MS or PhD in Electrical Engineering or a related field.
• Designing ultra-low-jitter PLLs (100 fs-class) in advanced CMOS at 5nm+.
• Deep PLL architecture and circuit design knowledge (phase detectors, charge pumps, loop filters).
• Strong understanding of phase noise, jitter, reference spurs, loop stability, and clock impact on SerDes.

Responsibilities

• Define end-to-end clocking architecture for next-gen SerDes (PLLs, clock generation, distribution).
• Lead ultra-low-jitter PLL design targeting <100 fs RMS jitter in 5nm+.
• Explore hybrid and digital PLL architectures and trade-offs (jitter, power, area).
• Mitigate coupling across multiple PLLs and clock-generation blocks (supply, substrate, EMI).
• Define clock distribution architectures including resonant clocking for power efficiency.
• Use EM tools to optimize inductors, resonant networks and interconnects.
• Develop SystemVerilog models and verification environments for PLLs.
• Collaborate with SerDes TX/RX, ADC, AMS layout, silicon validation teams.
• Drive silicon characterization, jitter analysis, and NOC-to-silicon correlation.

Skills

Clocking architecture

PLL design

PLL architecture

Multi-PLL coupling

Power-efficient clocking

EM analysis

Modeling & verification

Cross-functional leadership

Silicon execution & correlation

100G+ SerDes clocking

Resonant clock distribution

Clocking validation

Education

MS or PhD in Electrical Engineering

Tools

Cadence EMX

Ansys HFSS

Job description

Upscale, Inc. seeks a senior technical leader to define the clocking architecture for its next-generation SerDes platform. You will work across analog, mixed-signal, digital, layout and system teams to deliver exceptional timing performance in advanced CMOS at 5nm and below.

You will lead ultra-low-jitter PLL design, explore hybrid architectures, and drive silicon execution, verification, and correlation, with a focus on 100G+ per-lane SerDes clocking. This role is based in the Santa Clara area.