Principal Physical Verification Engineer

Broadcom Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

Medical, dental and vision plans

401(K) with company matching

ESPP

Paid holidays

Job summary

Broadcom's APD division seeks a Principal Physical Design Engineer to lead chip-level physical design and verification for advanced ASICs. This role requires hands-on verification, deep PD knowledge, and on-site collaboration at the San Jose campus.

You will work on 3nm/2nm nodes, drive floorplanning, DRC/LVS/PERC, and provide scripting-based flow improvements, with strong communication across teams.

Qualifications

• Bachelor's degree in Electrical or Electronics Engineering
• 12+ years of relevant experience in ASIC physical design
• Hands-on physical verification experience (LVS, DRC, ERC, PERC)
• Experience with 3nm/2nm nodes and chip integration
• Must work in San Jose site; on-site only
• Strong scripting (Python, Tcl, or Perl)

Responsibilities

• Execute chip-level physical verification and resolve issues
• Set up DRM runsets for advanced nodes and tool flows
• Manage rules for top-level floorplan, I/O and bump planning
• Resolve physical design issues related to chip integration and assembly
• Provide technical direction on verification methodologies (DRC/LVS/ERC/PERC)
• Develop best-practice guidelines for verification flows and optimizations

Skills

Physical verification

LVS DRC ERC PERC

EDA tools

Calibre Pegasus ICV

Python scripting

Top-level floorplan

Communication

On-site only

Tape-out experience

Density & Fill

Education

Bachelor's degree in Electrical or Electronics Engineering

Tools

Calibre

Pegasus

ICV

Job description

Principal Physical Design Engineer - ASIC Products Division (APD)

Location: San Jose, CA

Position Type: Full-Time

Broadcom's ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world's most innovative technology companies - spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders to co-design and manufacture complex, custom ASICs that power the modern digital backbone. The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges. We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.

Responsibilities

• Execution of Chip level Physical Verification & Issue resolution
• Work on setting up DRM runsets for advanced nodes and tool flows
• Manage and guide rules related to Top level Floorplan, I/O and bump planning
• Resolve physical design issues related to chip integration and assembly
• Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
• Develop best practice guidelines for physical verification flows and runtime optimizations

Preferred qualifications

• Hands-on experience in running physical verification (LVS, DRC, ERC, PERC)
• Experience with EDA tools and flows such as ICV, Calibre and Pegasus
• Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
• Experience in resolving chip level DRC/LVS/EMIR issues for advanced nodes and tape out experience
• Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities.
• Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules.
• Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules.
• Collaborate with physical design (P&R) to resolve critical top-level integration bottlenecks.
• Experience in scripting languages like Python, Tcl, or Perl
• Excellent verbal and written communication skills
• Must work in person at our San Jose site and no remote work allowed

Education and Experience Requirements

• Minimum: Bachelor's degree required in Electrical Engineering or Electronics Engineering
• 12+ Years of relevant experience

Compensation and Benefits

• The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
• Discretionary annual bonus
• Opportunity to receive not only a competitive new hire equity grant, but also annual equity awards
• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.

We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.

We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.