Senior Physical Design Engineer – 5nm/ASICs, On-Site SJ

Etched; San Jose (CA); On-site; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 monthly credit for waiving medical benefits

Housing subsidy of $2k per month

Relocation support for new hires

Wellness benefits including fitness and mental health

Daily lunch + dinner in-office

Job summary

A tech-focused company in San Jose is seeking exceptional Physical Design engineers to own block-level implementation and verification. Responsibilities include driving timing closure and PPA optimization, collaborating with RTL Designers, and supervising design flow improvements. Ideal candidates will have 5-10+ years of experience in physical design and familiarity with advanced design tools. Join a fully in-person team and enjoy comprehensive benefits, including a generous housing subsidy and health packages.

Qualifications

• 5-10+ years of experience in physical design.
• Experience with back-end design and timing closure on advanced process nodes (5nm and below).
• Familiarity with low power design methodology and power verification.

Responsibilities

• Supervise block-level implementation and verification.
• Drive timing closure and PPA optimization.
• Collaborate with RTL Designers to improve design feedback.

Skills

Physical Design expertise

Timing closure

Creativity

Python programming

Tools

Cadence (Innovus, Genus)

Synopsys (ICC2, Fusion Compiler)

Sign-off tools (PrimeTime, Tempus, Voltus)

Job description

A tech-focused company in San Jose is seeking exceptional Physical Design engineers to own block-level implementation and verification. Responsibilities include driving timing closure and PPA optimization, collaborating with RTL Designers, and supervising design flow improvements. Ideal candidates will have 5-10+ years of experience in physical design and familiarity with advanced design tools. Join a fully in-person team and enjoy comprehensive benefits, including a generous housing subsidy and health packages.