ASIC Physical Design Engineer – 3nm SoC, Equity Eligible

Broadcom Inc.; Fort Collins (CO); Hybrid; USD 120,000 - 170,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program

Employee Assistance Program

paid holidays

paid sick leave and vacation time

Job summary

Broadcom Inc. in Fort Collins, CO is seeking a Design Engineer focused on the physical implementation of high‑performance ASICs. Work across the RTL to GDSII flow, with exposure to 3 nm processes and sub‑micron design methodologies in a collaborative, fast-paced R&D setting.

You will use Cadence Innovus, Synopsys ICC2, and PrimeTime, partnering with multiple disciplines to deliver silicon solutions for AI, networking, and storage products.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Electronics Engineering.
• Experience with ASIC physical design concepts and CMOS design fundamentals.
• Strong analytical and debugging skills; quick learner of new tools and flows.

Responsibilities

• Contribute to physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).
• Support floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Perform physical verification (DRC/LVS) and signoff collaboration.
• Utilize EDA tools for design, implementation, and verification.
• Assist in timing analysis, power planning, IR/EM checks, and post-route optimization.
• Engage in RTL-to-GDSII flow and silicon bring-up activities.

Skills

VLSI design fundamentals

CMOS logic & digital circuits

ASIC physical design concepts

Analytical & debugging skills

UNIX/Linux environments

TCL scripting

Python or Perl

Education

Bachelor’s degree in Electrical or Electronics Engineering

Master’s degree in Electrical or Electronics Engineering

Tools

Cadence Innovus

Synopsys ICC2

PrimeTime

UNIX/Linux

TCL

Python

Perl

Job description

Broadcom Inc. in Fort Collins, CO is seeking a Design Engineer focused on the physical implementation of high‑performance ASICs. Work across the RTL to GDSII flow, with exposure to 3 nm processes and sub‑micron design methodologies in a collaborative, fast-paced R&D setting.

You will use Cadence Innovus, Synopsys ICC2, and PrimeTime, partnering with multiple disciplines to deliver silicon solutions for AI, networking, and storage products.