Advanced Physical Design and Verification Engineer (7036)

TSMC; San Jose (CA); Hybrid; USD 86,000 - 134,000; Full time

Job summary

TSMC is seeking an Advanced Physical Design and Verification Engineer in San Jose, CA, to lead DRC/LVS/ANTENNA checks, floorplan analysis, and timing ECOs for high-performance blocks. You will report to the Manager of Advanced Chip Implementation and join a team driving cutting-edge semiconductor design.

The role requires a Master’s in EE or CS, strong RTL/digital design experience, and hands-on use of major EDA tools. Hybrid schedule with 4 days in office in the South Bay area.

Qualifications

• Master’s degree in Electrical Engineering or Computer Science.
• Deep knowledge of hardware design including VLSI design, digital ICs, logic design, design for testing, computer architecture, and DDA.
• Experience in RTL coding, digital design and testing, physical implementation or design verification.
• In-depth knowledge of major EDA tools and design flows.
• Experience in Python and Perl/TCL language programming.
• Ability to work regularly at a customer site in the South Bay area.

Responsibilities

• DRC/LVS/ERC/ANTENNA analysis and clean up.
• Floorplan analysis and congestion solution.
• Power IR/EM analysis and fix.
• Signal EM/Noise analysis and fix.
• Physical verification sign off.
• Implement ECOs for timing closure.
• Customized Clock tree structure.
• May also perform floorplan, place and route.

Skills

RTL coding

Digital design

EDA tools

Python

Perl/TCL

Customer site work

Education

Master's degree in Electrical Engineering or Computer Science

Tools

EDA tools/flows

Job description

Overview Of Role

As a Advanced Physical Design and Verification Engineer, you will be responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, California and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office.

Overview Of Role

As a Advanced Physical Design and Verification Engineer, you will be responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, California and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office.

Responsibilities

• DRC/LVS/ERC/ANTENNA analysis and clean up
• Floorplan analysis and congestion solution
• Power IR/EM analysis and fix
• Signal EM/Noise analysis and fix
• Physical verification sign off
• Implement ECOs for timing closure
• Customized Clock tree structure
• May also perform floorplan, place and route

Minimum Qualifications

• Master’s degree in Electrical Engineering or Computer Science (Fresh graduate student with limited or no industry experience is welcome to apply).
• In depth knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
• Experiences in research projects or internship related to RTL coding, digital design and testing, physical implementation or design verification.
• In depth knowledge of major EDA tools/design flows
• Experience in Python, Perl/TCL language programming
• Ability to work regularly at a Customer site in the South Bay area

Preferred Qualifications

• TSMC N16 and below technology
• Chip level integration, and wire editing
• Low-power implementation methodology
• Able to independently complete Netlist-GDS P&R, signoff task
• Experience in block level implementation or chip integration and signoff

Company Description

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

Diversity statement

TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.

TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at [e-mail] . TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC Technology, Inc. may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC Technology, Inc. obtaining any export license or other approval that may be required by the U.S. Government.

Pay Transparency Statement

At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $85,500 and $134,000/yr. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual\'s skills, qualifications, education, experience and the position level and location.

TSMC’s total compensation package consists of market competitive pay, allowances, bonuses and comprehensive benefits. We also offer extensive development opportunities and programs.