Physical Design Verification Lead: Tapeout Specialist

TSMC - Taiwan Semiconductor Manufacturing Company Limited; San Jose (CA); Presencial; USD 180.000 - 280.000; Jornada completa

Descripción de la vacante

TSMC Technology Inc. is seeking a Technical Manager and Physical Design Verification Lead to drive end-to-end PD verification for CPU blocks at customer sites in the South Bay area.

You will lead verification efforts across DRC/LVS/ERC and CTS/Place & Route, ensuring robust silicon deliverables in collaboration with the STA team. Ideal candidates have 10–20 years in physical design and verification, strong scripting (TCL, Python), and experience with N7 or below technology nodes, with a proven

Formación

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10–20 years hands-on experience in physical implementation and verification roles.
• Proficiency with TCL, Perl and Python for automation.

Responsabilidades

• Lead end‑to‑end physical design verification for CPU blocks, culminating in production tapeouts.
• Collaborate with the STA team to implement ECOs for timing closure.
• Analyze and resolve Signal EM/Noise and Power IR/EM issues.
• Manage analysis and cleanup for DRC, LVS, ERC, and Antenna violations.
• Achieve final physical verification sign-off across design metrics.
• Oversee CTS implementation and advanced Place & Route strategies.
• Optimize block‑level floorplans and design partitioning.
• Provide technical leadership and mentorship to junior engineers.

Conocimientos

PD verification

CPU blocks

Team leadership

TCL scripting

Python scripting

Educación

Master's degree in EE/CE/CS

Herramientas

Innovus/ICC2

Calibre

Descripción del empleo

TSMC Technology Inc. is seeking a Technical Manager and Physical Design Verification Lead to drive end-to-end PD verification for CPU blocks at customer sites in the South Bay area.

You will lead verification efforts across DRC/LVS/ERC and CTS/Place & Route, ensuring robust silicon deliverables in collaboration with the STA team. Ideal candidates have 10–20 years in physical design and verification, strong scripting (TCL, Python), and experience with N7 or below technology nodes, with a proven