Senior Physical Design Engineer – Advanced Node ICs

Capgemini Engineering; Santa Clara (CA); On-site; USD 82,000 - 193,000; Full time

Benefits offered by this job

Paid time off (PTO)

Medical, dental, vision

401(k) retirement plans

Job summary

Capgemini Engineering in Santa Clara, CA is seeking a Physical Design Engineer to drive complex digital and mixed-signal IC implementation from floorplanning to tape-out.

The role emphasizes hands-on physical design across advanced process nodes (3nm–7nm), power-grid and clock constraints, LVS/DRC verification, and cross-functional collaboration with design, layout, and verification teams to meet performance, power and area targets.

Qualifications

• Must have 10+ years of Physical Design experience with complex digital or mixed-signal IC implementation.
• Strong knowledge of physical design flows: floor planning, CTS, P&R, synthesis, and closure.
• Experience developing power-grid strategies and high-speed constraints.
• Familiarity with LVS/DRC at chip and block levels.
• Exposure to CDC and STA methodologies and parasitic timing effects.
• Experience with advanced nodes (7nm–2nm) is highly preferred.

Responsibilities

• Lead or support physical design activities across floorplanning, placement, CTS, routing and sign-off.
• Develop power-grid strategies and high-speed clock constraints to optimize performance, power and area.
• Perform physical verification and debug LVS/DRC issues at chip and block levels.
• Collaborate with design, layout, verification and timing teams throughout the IC lifecycle.
• Support CDC, STA, parasitic-aware simulations and timing closure activities.
• Assist tape-out readiness, foundry interaction and IC product development alignment.
• Evaluate tradeoffs in power, area, performance and layout complexity for advanced nodes (3nm/5nm/7nm).

Skills

10+ years Physical Design experience

Floor planning

Clock tree synthesis

Place and route

Physical verification (LVS/DRC)

Power-grid strategies

High-speed clock constraints

CDC / STA awareness

Parasitic-aware timing

EDA tools (Virtuoso, Calibre, RedHawk)

Tools

Virtuoso

Calibre

RedHawk

Job description

Capgemini Engineering in Santa Clara, CA is seeking a Physical Design Engineer to drive complex digital and mixed-signal IC implementation from floorplanning to tape-out.

The role emphasizes hands-on physical design across advanced process nodes (3nm–7nm), power-grid and clock constraints, LVS/DRC verification, and cross-functional collaboration with design, layout, and verification teams to meet performance, power and area targets.