Senior Physical Design Engineer – Advanced Node

Capgemini Engineering; Santa Clara (CA); On-site; USD 82,000 - 193,000; Full time

Benefits offered by this job

Paid time off

Health benefits

Retirement plan

Employee assistance programs

Job summary

Capgemini Engineering in Santa Clara, CA is seeking a seasoned Physical Design Engineer to advance complex digital/mixed-signal IC implementations through floor planning, placement, CTS, routing, and tape-out readiness. You will optimize power, area, and performance while collaborating with cross-functional teams across the design lifecycle.

Key qualifications include 10+ years in physical design, proficiency with LVS/DRC, CDC, STA, and parasitic delay analyses, and hands-on use of Virtuoso,

Qualifications

• 10+ years of experience in Physical Design, with hands-on IC implementation.
• Strong knowledge of physical design flows including floor planning, clock tree synthesis, place and route, and design closure.
• Experience with power-grid strategies and high-speed clock constraints to optimize performance, power and area.
• Familiarity with LVS/DRC, CDC, static timing analysis, and parasitic delay.
• Exposure to mixed-signal environments and analog/layout interaction.
• Hands-on experience with EDA tools such as Virtuoso, Calibre, RedHawk.

Responsibilities

• Lead or support physical design activities, including floor planning, placement, clock tree synthesis, routing, and physical-aware synthesis.
• Develop and implement power-grid strategies, high-speed clock constraints, and design specifications to support performance, power, and area goals.
• Perform physical design verification and debug LVS and DRC issues at both chip and block levels.
• Collaborate with design, layout, verification, timing, and methodology teams to address implementation challenges across the design lifecycle.
• Support CDC, static timing analysis, parasitic-aware simulations, and timing closure activities using relevant EDA tools and methodologies.
• Contribute to tape-out readiness, including design sign-off, foundry interaction, and alignment with IC product development requirements.
• Evaluate design tradeoffs related to power consumption, area, performance, layout complexity, and technology limitations for advanced process nodes(3nm /5nm/7nm

Skills

Physical design

Floor planning

Clock tree synthesis

Place and route

Design closure

Power-grid strategies

CDC

Static timing analysis

Parasitic delay

EDA tools

Tools

Virtuoso

Calibre

RedHawk

Job description

Capgemini Engineering in Santa Clara, CA is seeking a seasoned Physical Design Engineer to advance complex digital/mixed-signal IC implementations through floor planning, placement, CTS, routing, and tape-out readiness. You will optimize power, area, and performance while collaborating with cross-functional teams across the design lifecycle.

Key qualifications include 10+ years in physical design, proficiency with LVS/DRC, CDC, STA, and parasitic delay analyses, and hands-on use of Virtuoso,