Senior Physical Design Lead – Timing & Floorplanning

Mirafra Technologies; United States; Presencial; USD 140.000 - 190.000; Jornada completa

Descripción de la vacante

Mirafra Technologies seeks an experienced Physical Design Engineer to lead and implement physical design across high-volume consumer devices and satellite-related projects. You will own end-to-end physical design methodologies, drive timing closure, and collaborate with cross-functional teams to deliver robust chip implementations.

The role requires 8+ years with a Bachelor's (or 10+ with a Master’s) in Electrical Engineering, deep hands-on expertise with Innovus and Cadence flows, TCL

Formación

• Bachelor's with 8+ years of hands-on experience in physical design
• Master's with 10+ years of hands-on experience in physical design
• Experience across 40nm to 7nm nodes and end-to-end flow ownership
• Proficiency with TCL scripting is required; Python is a plus

Responsabilidades

• Lead and implement physical design for chips across multiple nodes
• Perform block- and top-level physical implementation
• Drive floorplanning including multi-power domain design, PG planning, and clock tree implementation
• Collaborate with Design, IP, and Library teams and interface with stakeholders
• Conduct physical verification at block and chip levels
• Perform IR drop analysis and power integrity checks
• Develop methods and flows for physical design and timing closure
• Coordinate with Synthesis, STA, and RTL teams to meet power and timing targets
• Support ESD, IO padring, and analog integration; packaging knowledge preferred

Conocimientos

Electrical engineering expertise

Timing closure

Scripting (TCL)

Python (pleasant)

Educación

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Herramientas

Innovus

VCLP

Formality

LEC

Calibre

Timing closure tools

Cadence Innovus

Descripción del empleo

Mirafra Technologies seeks an experienced Physical Design Engineer to lead and implement physical design across high-volume consumer devices and satellite-related projects. You will own end-to-end physical design methodologies, drive timing closure, and collaborate with cross-functional teams to deliver robust chip implementations.

The role requires 8+ years with a Bachelor's (or 10+ with a Master’s) in Electrical Engineering, deep hands-on expertise with Innovus and Cadence flows, TCL