Senior Physical Design Engineer

Mirafra Technologies; United States; In loco; USD 140.000 - 190.000; Tempo pieno

Descrizione del lavoro

Mirafra Technologies seeks an experienced Physical Design Engineer to lead and implement physical design across high-volume consumer devices and satellite-related projects. You will own end-to-end physical design methodologies, drive timing closure, and collaborate with cross-functional teams to deliver robust chip implementations.

The role requires 8+ years with a Bachelor's (or 10+ with a Master’s) in Electrical Engineering, deep hands-on expertise with Innovus and Cadence flows, TCL

Competenze

• Bachelor's with 8+ years of hands-on experience in physical design
• Master's with 10+ years of hands-on experience in physical design
• Experience across 40nm to 7nm nodes and end-to-end flow ownership
• Proficiency with TCL scripting is required; Python is a plus

Mansioni

• Lead and implement physical design for chips across multiple nodes
• Perform block- and top-level physical implementation
• Drive floorplanning including multi-power domain design, PG planning, and clock tree implementation
• Collaborate with Design, IP, and Library teams and interface with stakeholders
• Conduct physical verification at block and chip levels
• Perform IR drop analysis and power integrity checks
• Develop methods and flows for physical design and timing closure
• Coordinate with Synthesis, STA, and RTL teams to meet power and timing targets
• Support ESD, IO padring, and analog integration; packaging knowledge preferred

Conoscenze

Electrical engineering expertise

Timing closure

Scripting (TCL)

Python (pleasant)

Formazione

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Strumenti

Innovus

VCLP

Formality

LEC

Calibre

Timing closure tools

Cadence Innovus

Descrizione del lavoro

We are seeking an experienced Physical Design Engineer to lead and implement physical design across a range of high-volume consumer devices and satellite-related projects. This role involves end-to-end physical implementation, collaboration with cross-functional teams, and ownership of physical design methodologies and timing closure.

Key Responsibilities:

• Lead and implement physical design for chips across process nodes ranging from 40nm to 7nm
• Perform block-level and top-level physical implementation
• Drive floorplanning activities including multi-power domain design, power grid (PG) planning, block shaping, and clock tree implementation
• Interface with internal and external stakeholders, including Design, IP, and Library teams
• Conduct physical verification at block and chip level
• Perform static and dynamic IR drop analysis, as well as signal and power
• Develop methodologies and flows for physical design and timing closure
• Collaborate with Synthesis, STA, and RTL design teams to meet physical implementation and power intent requirements
• Support ESD, IO padring, and analog integration; experience with packaging types such as flip-chip and WLCSP is preferred

Required Qualifications:

• Bachelor's degree in Electrical Engineering with 8+ years of experience, OR Master's degree in Electrical Engineering with 10+ years of experience
• Extensive hands-on experience with tools such as Innovus, VCLP, Formality, LEC, Calibre, and timing closure tools
• Strong expertise with Cadence Innovus (required)
• TCL scripting experience (required); Python is a plus
• Knowledge of physical design flows and methodologies