Senior Physical Design Engineering Lead

CyberCoders; San Jose (CA); On-site; USD 500,000 - 800,000; Full time

Job summary

CyberCoders in Silicon Valley, CA seeks Principal and Master Physical Design Engineering Leads to guide customer ASIC programs and deliver highly complex designs. This senior level role is hands-on (about 80%) with some technical leadership to drive outcomes for AI and HPC projects.

You will coordinate end-to-end tapeouts, optimize PPA, and collaborate with EDA teams. The role emphasizes deep physical design expertise, advanced node flows, and clear communication across customers and internal

Qualifications

• Hands-on experience in physical design or STA, with EDA tools and flows.
• Multiple tape-outs at advanced process nodes.
• Ability to analyze PPA tradeoffs across library components, architectures, and implementation strategies.
• Thorough understanding of low power design techniques and power management.
• Programming or scripting experience.
• Excellent communication skills.

Responsibilities

• Driving end-to-end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring-up, and production.
• Managing physical design validation flows to ensure incoming customer netlists meet strict tape-out quality requirements.
• Hosting informative sessions with technical experts and advising customer teams on EDA best practices, design flows, and methodologies.
• Identifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teams.

Skills

Hands-on physical design/STA

Multiple tape-outs

PPA tradeoffs analysis

Low power design techniques

Programming/scripting

Excellent communication

Tools

EDA tools

Job description

Principal and Master Physical Design Engineering Leads (2 Openings)

Total packages: $500,000 to $800,000 (Base + Bonus + Stock)

Locations: Sillicon Valley, CA

The Role / Responsibilities

As a senior technical leader, (NOTE: prior leadership experience NOT required) you will guide customer ASIC programs and ensure successful delivery of highly complex designs. (Approximately 80% hands on, 20% technical leadership).

Top Reasons to Work With Us

Join the best and brightest in the field: lead complex customer engagements and influence next-generation chip development, tackling the industry's most challenging ASIC challenges and powering tomorrow's AI and high-performance computing systems.

Your responsibilities will include:

• Driving end-to-end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring-up, and production
• Managing physical design validation flows to ensure incoming customer netlists meet strict tape-out quality requirements
• Hosting informative sessions with technical experts and advising customer teams on EDA best practices, design flows, and methodologies
• Identifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teams

Essential Skills Over 10+ Years of Experience:

• Hands-on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packaging
• Multiple tape-outs at advanced process nodes
• Ability to analyze PPA tradeoffs across library components, architectures, and implementation strategies
• Thorough understanding of low power design techniques and power management
• Programming or scripting experience
• Excellent communication skills

A Plus if you Have:

• Exposure to SERDES communication protocols
• Experience in logic design, chip architecture, microarchitecture, Verilog RTL development, front-end verification, DRC, and logic synthesis
• Knowledge of DFT methods including scan, memory BIST, and repair