Senior Physical Design Engineer (Top-level)

Central Business Solutions Inc.; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Central Business Solutions Inc. seeks a Physical Design Engineer (Top-level) to join the ASIC Products Division in San Jose, onsite five days a week. The role focuses on bringing nets to silicon tape-out with top-level PD, timing, and verification expertise.

Responsibilities include physical design, timing closure, EM/IR analysis, clock tree synthesis, floorplanning, and RTL collaboration. Bachelor’s degree in EE is required, with strong communication skills.

Qualifications

• Bachelor’s degree in Electrical or Electronics Engineering.
• Experience in physical design RTL to tape-out.
• Proficiency with EDA tools.
• Strong verbal and written communication.

Responsibilities

• Execution of Physical Design, Physical Verification, and Timing Closure.
• Timing closure through various methods and top-level STA experience.
• EM/IR Analysis, Place and Route.
• Clock Tree Synthesis with clock trees and skew balancing techniques.
• Floor-planning and Layout for top-level designs.
• Flow and Methodology Development.
• Collaborating with IC Design RTL Engineers.

Skills

TCL scripting

PERL scripting

Full PD cycle experience

Communication skills

Education

Bachelor's degree in Electrical Engineering or Electronics Engineering

Tools

EDA Tools

Job description

Title: Physical Design Engineer (Top-level)

Location: San Jose , CA (100% Onsite)

Location for the role is on-site at San Jose, 5-days a week

Type: FTE Permanent role

Job Description:

Client is searching for a Physical Design Engineer to join the ASIC Products Division.

This position involves working with the latest technology to continue driving next generation AI designs. This position will require in-depth knowledge and expertise in Physical Design aspects of taking Netlist to silicon tape-out.

Responsibilities include, but are not limited to the following:

Execution of Physical Design, Physical Verification, and Timing Closure

Timing closure through various methods and strategies; preferable in-depth experience in top-level STA

EM/IR Analysis, Place and Route

Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques

Floor-planning and Layout; preferable in-depth experience in top-level floorplanning

Flow and Methodology Development

Collaborating with IC Design RTL Engineers

Required attributes:

TCL/PERL Scripting

Proficiency in related EDA Tools

Full physical design cycle experience: RTL to Tape-out

Excellent verbal and written communication skills

Education and Experience Requirements:

Minimum:

Bachelor’s degree required in Electrical Engineering or Electronics Engineering