Principal Physical Design Engineer

Celero Communications, Inc.; United States; Remote; USD 200,000 - 300,000; Full time

Job summary

Celero Communications, Inc. is seeking a Senior/Principal Physical Design Engineer to own the physical implementation of SoCs or advanced digital blocks. You will drive floorplanning, CTS and power grid design to optimize performance and reliability.

Lead convergence with frontend teams, run STA and physical verifications, and fix DRC/LVS issues. Build automated flows with Tcl/Python/Perl to improve flow robustness and tapeout readiness.

Qualifications

• 7+ to 15+ years of ASIC physical design experience for SoCs or complex blocks.
• Experience with advanced nodes and tapeout flow in 7/5/3nm technology.
• Strong background using Cadence tools for physical design flows.
• Proficiency in physically aware synthesis and EM/IR analysis/cleanup.

Responsibilities

• RTL-to-GDSII execution: own physical implementation of SoCs or complex blocks.
• Floorplanning, bump planning, power grid design and CTS to optimize performance.
• Convergence: resolve timing, congestion, EM/IR issues with frontend designers.
• Signoff & verification: STA, physical verification, fix DRC/LVS violations.
• Automation: develop flows with Tcl/Python/Perl to boost robustness.
• Cross-functional leadership with architects, logic and analog teams for tapeout.

Skills

ASIC PD Experience

Tapeout 7nm/5nm/3nm

EM/IR cleanup

Tools

Innovus

Tempus

Voltus

Pegasus

Calibre

Job description

Senior/Principal Physical Design Engineer

Core Responsibilities

• RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
• Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
• Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.

Key Qualifications

• Experience: 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
• Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre).
• Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $200,000 to $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)