Senior Physical Design Engineer: Tapeouts & Equity

Bolt Graphics; Sunnyvale (CA); On-site; USD 200,000 - 220,000; Full time

Benefits offered by this job

Medical, Dental, & Vision - 100% covered premiums

Equity - Stock Options

401(k) match

Job summary

A semiconductor startup in California is seeking a Staff/Senior Staff Physical Design Engineer to lead physical design implementations. The role requires 8-12 years of experience in ASIC design, with a focus on timing, power, and area optimizations. Candidates should have strong expertise in STA and familiarity with industry-standard tools like Synopsys ICC2 and Cadence Innovus. The compensation range is $200,000–$220,000 per year, and benefits include fully covered medical premiums and equity options.

Qualifications

• 8–12 years of experience in ASIC physical design.
• Proven experience in full-chip or large block implementation.
• Strong expertise in timing closure and physical verification.

Responsibilities

• Drive full-chip or block-level physical implementation from netlist to GDSII.
• Optimize designs for power, performance, and area (PPA).
• Collaborate with RTL and architecture teams for design convergence.

Skills

ASIC physical design

Static Timing Analysis (STA)

Floorplanning

Problem-solving

Scripting in Python/TCL

Routing

Education

Bachelor’s/Master’s degree in Electrical Engineering

Tools

Synopsys ICC2

Cadence Innovus

Job description

A semiconductor startup in California is seeking a Staff/Senior Staff Physical Design Engineer to lead physical design implementations. The role requires 8-12 years of experience in ASIC design, with a focus on timing, power, and area optimizations. Candidates should have strong expertise in STA and familiarity with industry-standard tools like Synopsys ICC2 and Cadence Innovus. The compensation range is $200,000–$220,000 per year, and benefits include fully covered medical premiums and equity options.