Senior CPU Physical Design Engineer: RTL to GDS Tape-out

NUVACORE, Inc.; Austin, Northern (TX, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

NUVACORE, Inc. is seeking a CPU Physical Design Engineer to drive end-to-end design closure from RTL to GDS/tape-out while optimizing power, performance, and area. You will coordinate with CAD, RTL/μ-arch, and partner teams to ensure timely design cycle progress and PPAs.

The role requires strong experience in PD signoff and DFT timing, plus excellent collaboration and communication abilities to influence tools and methodologies across the team.

Qualifications

• Hold a BS or MS degree in Electrical Engineering or related field with 5+ years (IC) or 12+ years (Lead) CPU PD experience.
• Proficient in industry-standard EDA tools and CPU design workflows.
• Track record of delivering production-level designs through tape-out.
• Experience in PPA optimization across CPU units and design blocks.
• Strong understanding of end-to-end physical design closure including signoff domains and DFT timing constraints.
• Excellent communication and cross-team collaboration skills.

Responsibilities

• Evaluate RTL and micro-architecture designs, providing feasibility assessments and actionable feedback.
• Drive end-to-end design closure from RTL to GDS/tape-out meeting PPAs (Power, Performance, Area & Schedule).
• Coordinate with CAD, RTL/μ-arch, and partner teams to ensure seamless execution through the design cycle.
• Lead and influence Tools, Flows, and Methodology (TFM) adoption to boost design efficiency and establish best practices.

Skills

CPU PD

PPA optimization

End-to-end PD

Team collaboration

Python/TCL/Perl

EDA tools

Communication

Education

BS or MS in Electrical Engineering

Tools

EDA tools suite

Python

Perl

TCL

Agentic AI tools

Job description

NUVACORE, Inc. is seeking a CPU Physical Design Engineer to drive end-to-end design closure from RTL to GDS/tape-out while optimizing power, performance, and area. You will coordinate with CAD, RTL/μ-arch, and partner teams to ensure timely design cycle progress and PPAs.

The role requires strong experience in PD signoff and DFT timing, plus excellent collaboration and communication abilities to influence tools and methodologies across the team.