Senior Physical Design Engineer (RTL-to-GDS)

TSMC; San Jose (CA); Hybrid; USD 110,000 - 160,000; Full time

Job summary

TSMC is seeking a Physical Design Engineer in San Jose to drive the complete RTL-to-GDS flow, including synthesis, floorplanning, placement, routing, CTS, STA, and signoff. The role operates on a hybrid schedule with four days in the office.

You will work on block-level implementation, ECOs for timing, and signoff, leveraging expertise with major EDA flows and TSMC technologies to deliver production tapeouts. Strong scripting skills are a plus.

Qualifications

• Master’s degree in Electrical/Computer Science Engineering is required.
• Experience with netlist-GDS physical implementation and strong EDA tool knowledge.
• Experience with TSMC N16 or below technology and block-level signoff.

Responsibilities

• Complete entire physical implementation of the block level and tapeout production chip.
• Perform block-level floorplanning and analyze floorplan quality.
• Customize clock tree structure and Place & Route.
• Implement ECOs for timing closure.
• Signal EM/Noise and Power IR/EM analysis and fixes.
• DRC/LVS/ERC/ANTENNA analysis and cleanup.
• Achieve physical verification sign-off.

Skills

Netlist-GDS flow experience

Perl/TCL scripting

Block level implementation

EDA tool familiarity

Education

Master’s degree in Electrical/Computer Science Engineering

Tools

Major EDA tools/design flows

TSMC N16 or below technology

Job description

TSMC is seeking a Physical Design Engineer in San Jose to drive the complete RTL-to-GDS flow, including synthesis, floorplanning, placement, routing, CTS, STA, and signoff. The role operates on a hybrid schedule with four days in the office.

You will work on block-level implementation, ECOs for timing, and signoff, leveraging expertise with major EDA flows and TSMC technologies to deliver production tapeouts. Strong scripting skills are a plus.