Senior Physical Design Engineer - Low-Power MCU/SoC

Microchip Technology Inc; Chandler (AZ); On-site; USD 120,000 - 180,000; Full time

Job summary

Microchip Technology Inc is seeking a skilled Physical Design Engineer to drive die size estimation, floorplanning, placement, and timing closure for DSPIC designs. You will collaborate with cross-functional teams to ensure reliable sign-off, power integrity, and high-quality tapeouts of microcontroller-based SOC designs.

The role emphasizes low-power, high-performance PD, flow development, and close coordination with IP and CAD vendors to deliver robust silicon across global projects.

Qualifications

• Bachelor's or Master's in Electrical/Electronic Engineering or equivalent.
• Minimum 5 years of hands-on experience in Physical Design.
• Advanced knowledge of place and route and low-power PD flows.
• Proficiency with industry tools such as Innovus, Fusion Compiler, Calibre, Redhawk, Starrcxt.
• Strong TCL, PERL, and Shell scripting; HDL experience with Verilog/VHDL.
• Excellent analytical, debugging, and communication skills.
• Independent and self-motivated with team collaboration.

Responsibilities

• Perform floorplanning, placement, and routing with emphasis on timing, area, and power.
• Lead clock tree synthesis, balancing, and timing closure.
• Conduct power integrity and IR drop analyses and signoff.
• Develop and refine PD flow and methodology with documentation.
• Interface with IP teams and CAD vendors to resolve issues.
• Collaborate with synthesis, DFT, and cross-functional teams for tapeout readiness.

Skills

TCL scripting

Perl scripting

Shell scripting

Verilog

VHDL

Analytical thinking

Communication

Education

Bachelor's or Master's in Electrical/Electronic Engineering

Tools

Innovus

Fusion Compiler

Calibre

Redhawk

Starrcxt

Job description

Microchip Technology Inc is seeking a skilled Physical Design Engineer to drive die size estimation, floorplanning, placement, and timing closure for DSPIC designs. You will collaborate with cross-functional teams to ensure reliable sign-off, power integrity, and high-quality tapeouts of microcontroller-based SOC designs.

The role emphasizes low-power, high-performance PD, flow development, and close coordination with IP and CAD vendors to deliver robust silicon across global projects.