Physical Design Engineer

ACL Digital; Texas; On-site; USD 120,000 - 180,000; Full time

Job summary

ACL Digital is seeking an experienced Physical Design Engineer to join our semiconductor engineering team. You will contribute to advanced physical design methodologies for high-performance, low-power SoCs and IP blocks, from synthesis through tapeout, collaborating across architecture, RTL, DFT, and CAD groups.

The role emphasizes floorplanning, power planning, CTS, routing, timing closure, SI analysis, and design signoff, supporting multiple programs in GPU, AI, and compute domains.

Qualifications

• Bachelor’s or higher in science/engineering with ASIC design experience.
• Experience with digital ASIC physical implementation methodologies.
• Understanding of tradeoffs between power, performance, area, and timing.
• Experience in Linux/Unix environments.
• Programming or scripting with Python, Tcl, Perl, Shell, or similar.

Responsibilities

• Perform floorplanning, power planning, place and route, clock tree synthesis and timing closure.
• Conduct signal integrity analysis, physical verification, ECO implementation and signoff.
• Collaborate with architecture, RTL, DFT, CAD and product teams to deliver designs from synthesis to tapeout.
• Contribute to long-term design optimization and low-power implementation techniques.

Skills

Digital ASIC

Physical design

Python scripting

Linux environments

Problem solving

Debugging

Education

Bachelor's degree in Science

Master's degree in Science

PhD in Science

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime

RC extraction tools

Job description

We are looking for an experienced and passionate Physical Design Engineer to join our semiconductor engineering team!

Description:

We are seeking highly motivated Physical Design Engineers across multiple career levels to join our growing ASIC implementation team. In this role, you will contribute to the development and execution of advanced physical design methodologies for complex, high performance, low-power SoCs and IP blocks.

You will work closely with architecture, RTL, DFT, verification, CAD, and product engineering teams to implement and deliver industry leading designs from synthesis through final tapeout.

The ideal candidate possesses strong technical expertise in physical implementation, timing closure, low-power design techniques, automation, and design optimization.

Depending on experience and demonstrated technical leadership, candidates may be considered for Engineer, Senior Engineer, Staff Engineer, or Principal Engineer opportunities.

Physical Design responsibilities include floorplanning, power planning, place and route, clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff activities.

The role supports advanced SoC and core design programs across GPU, Multimedia, AI, Compute, Connectivity, Modem, DDR, Audio, and other next-generation technologies.

Minimum Qualifications:

• Bachelor's degree in Science OR Master's degree in Science, Engineering, OR PhD in Science, Engineering, or related field and experience of ASIC design, verification, validation, integration, or related work experience.
• Experience with digital ASIC physical implementation methodologies.
• Understanding of power, performance, area, timing, and physical design tradeoffs.
• Experience working in Linux/Unix environments.
• Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages. Strong analytical, problem-solving, and debugging skills.

Preferred Qualifications:

• Experience with complete Physical Design Flow from synthesis through tapeout.
• Physical design expertise including floorplanning, power planning, placement, CTS, routing, timing optimization, and closure
• Experience using Cadence Innovus and/or Synopsys Fusion Compiler.
• Static Timing Analysis and timing closure experience using Synopsys PrimeTime.
• Knowledge of MMMC implementation methodologies and advanced-node design closure.
• Experience with DFT-aware implementation and functional timing constraints.
• Experience with RC extraction, signal integrity analysis, cross-talk analysis, ECO implementation, and formal verification.
• Experience with low-power implementation techniques, UPF methodologies, and power domain analysis.
• Strong communication, collaboration, and technical leadership capabilities.

Technical Expertise Areas Successful candidates may possess expertise in one or more of the following areas: