High-Speed ASIC Design Engineer RTL & Timing

Lumicity; San Jose (CA); On-site; USD 100,000 - 150,000; Full time

Job summary

Lumicity, located on-site in San Jose, CA, is offering an exciting opportunity to work on high-speed digital integrated circuits. The successful candidate will engage in High-Speed Digital Design, RTL Design, and Synthesis for next-generation products. Required qualifications include a B.S. or M.S. in Electrical Engineering and extensive experience with Verilog or SystemVerilog, as well as EDA tools like Cadence and Synopsys. Ideal candidates will have a strong foundation in Digital ASIC Design and scripting experience with Python, TCL, or Perl.

Qualifications

• Experience working with Hardware Description Languages such as Verilog or SystemVerilog.
• Strong background in Digital ASIC Design understanding complete ASIC design flow.
• Must have worked with EDA tools like Cadence or Synopsys.

Responsibilities

• Work on High-Speed Digital Design and RTL Design.
• Participate in Clock Domain Crossing, Synthesis and Timing Closure.

Skills

Verilog

SystemVerilog

Digital ASIC Design

Cadence EDA tools

Synopsys EDA tools

Python

TCL

Perl

Education

B.S. or M.S. in Electrical Engineering

Tools

Tempus

PrimeTime

Genus

Design Compiler

Formality

JasperGold

Job description

Lumicity, located on-site in San Jose, CA, is offering an exciting opportunity to work on high-speed digital integrated circuits. The successful candidate will engage in High-Speed Digital Design, RTL Design, and Synthesis for next-generation products. Required qualifications include a B.S. or M.S. in Electrical Engineering and extensive experience with Verilog or SystemVerilog, as well as EDA tools like Cadence and Synopsys. Ideal candidates will have a strong foundation in Digital ASIC Design and scripting experience with Python, TCL, or Perl.