Physical Design Engineer

Apple Inc.; San Francisco (CA); On-site; USD 150,400 - 277,600; Full time

Job summary

Apple Inc. in the San Francisco Bay Area seeks a Physical Design Engineer focused on high-performance PHYs from RTL to GDSII. You will collaborate with architecture, CAD, timing, and logic teams to deliver robust PHY designs in a demanding environment.

The role emphasizes deep PD knowledge, clock and power grid specifications, and scripting expertise to optimize flows. A BS in EE with 3+ years experience is preferred, with competitive base pay and full benefits.

Qualifications

• Bachelors of Science in Electrical Engineering required.
• 3+ years experience preferred in physical design.
• Deep understanding of PHY/SOC design elements and timing.

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor-plan with pin placement and power grid.
• Develop high-performance, low-power clock network guidelines.
• Perform block-level place and route to meet timing, area and power.
• Create and implement ECOs for timing, noise and EM/IR issues.
• Run PD verification and fix LVS/DRC violations with teams.

Skills

Physical Design

High PHY

Verilog HDL

Floorplanning

Place & Route

Power-Grid Design

STA/Extraction

Scripting: Perl/Tcl

Education

Bachelor's degree in Electrical Engineering

Tools

Physical Design Tools

Job description

San Francisco Bay Area, California, United States - Hardware

Overview

Physical Design Engineer – PHY focusing on high-performance and low-power physical design from RTL to GDSII delivery. Work with architecture, CAD, timing, and logic design teams to deliver outstanding PHY designs.

Description

As a Physical Design Engineer you will contribute to all phases of physical design of high performance PHYs from RTL to final GDSII delivery. Your responsibilities include but are not limited to:

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement, partitions and power grid.
• Develop and validate high-performance low-power clock network guidelines.
• Perform block level place and route and close the design to meet timing, area and power constraints.
• Generate and implement ECOs to fix timing, noise and EM IR violations.
• Run physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing CAD and physical design methodologies for correct-by-construction designs.
• Assist in flow development for chip integration.

Minimum Qualifications

• Bachelors of Science in Electrical Engineering and 3+ years experience preferred.

Preferred Qualifications

• Deep design experience in high PHY and/or SOC designs.
• Deep knowledge of industry standards and practices in Physical Design, including physically aware synthesis, floor-planning, and place & route.
• Experience in developing and implementing power-grid and clock specifications.
• Strong understanding of all aspects of physical construction, integration and physical verification.
• Knowledge of basic SoC architecture and HDL languages like Verilog to collaborate with logic design team for timing fixes.
• Power user of industry-standard Physical Design & Synthesis tools.
• Deep understanding of scripting languages such as Perl/Tcl, solid understanding of extraction and STA methodology and tools.
• Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.

Compensation & Benefits

Base pay range: $150,400 - $277,600, dependent on skills, qualifications, experience, and location.

Apple employees may become shareholders through discretionary stock programs and participate in an Employee Stock Purchase Plan.

Benefits include comprehensive medical and dental coverage, retirement benefits, product discounts, free services, and tuition reimbursement for educational expenses.

Additional incentives may include discretionary bonuses or commission payments and relocation assistance.