Senior Physical Design Engineer – High-Performance ASICs

Tachyum; Sunnyvale (CA); On-site; USD 150,000 - 300,000; Full time

Benefits offered by this job

Competitive salary

Equity and benefits

International environment

Professional development

Collaborative work environment

Bleeding edge technology

Job summary

Tachyum is seeking a Physical Design Engineer in Sunnyvale, CA to drive PD for ultra‑high performance chips. You will collaborate with RTL teams, perform floor‑planning, routing, and timing closure, and contribute to clock and power integrity strategies.

The role requires strong Verilog know‑how, ASIC flow experience, and a track record mentoring engineers. Expect a dynamic, cutting-edge environment with competitive compensation and equity.

Qualifications

• Member of core team responsible for crafting and timely delivery of PD partitions.
• Strong communication and interpersonal skills to work with our global design team.
• Successful track record of mentoring junior engineers and interns (plus).
• More than 5 years of experience in high-performance semiconductor designs.
• Verilog knowledge and an understanding of ASIC design flow.
• Expertise in logic synthesis, prototyping, timing analysis, floor-planning.
• Expertise in flow automation (Perl, Tcl, Python) and understanding of full PD methodology.
• Experience with Innovus on 7nm or lower technology nodes.
• A background in computer architecture is desirable.
• Ability to learn new technologies and apply that knowledge quickly.
• Proven track record demonstrating the ability to meet project milestones and deadlines.
• BS or MS Degree in Electrical Engineering or Computer Science.
• Familiarity with basic synthesizable RTL designs (flops, FIFOs, clock domain crossing) is a plus.
• Strong familiarity with PCIe, Ethernet (100G and above), DDR4.
• Ability to create regression scripts to run individual and batch jobs on grid.

Responsibilities

• Responsible for implementation of ultra‑high performance and low‑power data processing chip.
• Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs.
• Floor‑planning, experimenting with placement and routing techniques for better PPA.
• Do timing closure for very high frequency designs with possible hand placement of logic when needed.
• Help define low‑latency/low‑skew clock tree methodology/design.
• Help define appropriate power grid structures to meet EM/IR goals.
• Scripting and automating flows to improve turn‑around times.

Skills

5+ years experience

Verilog knowledge

ASIC design flow

Timing analysis

Floor planning

Power/EM/IR

Scripting (Python, Perl, Tcl)

Regression scripting

PCIe/Ethernet/DDR4 familiarity

Mentoring

Education

BS or MS Degree in Electrical Engineering or Computer Science

Tools

Innovus

Perl

Tcl

Python

Job description

Tachyum is seeking a Physical Design Engineer in Sunnyvale, CA to drive PD for ultra‑high performance chips. You will collaborate with RTL teams, perform floor‑planning, routing, and timing closure, and contribute to clock and power integrity strategies.

The role requires strong Verilog know‑how, ASIC flow experience, and a track record mentoring engineers. Expect a dynamic, cutting-edge environment with competitive compensation and equity.