Senior Physical Design Engineer for High-Performance ASICs

Tachyum; Las Vegas (NV); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive salary

Benefits package

Career development

International environment

Bleeding-edge technology

Job summary

Tachyum in Las Vegas seeks a senior IC design engineer to drive ultra-high performance, low-power data-processing chips. You will work with RTL teams to meet aggressive PPA targets and contribute to floorplanning, timing closure, and clock-tree design.

The role requires 5+ years in semiconductor design, Verilog expertise, and experience with Innovus. Strong collaboration skills and willingness to mentor junior engineers are essential.

Qualifications

• 5+ years in high performance semiconductor designs.
• BS or MS degree in Electrical Engineering or Computer Science.
• Verilog knowledge and ASIC design flow understanding.
• Proficiency with Innovus or similar P&R tools.
• Strong communication skills and ability to mentor juniors.

Responsibilities

• Implement ultra-high performance, low power data processing chip.
• Collaborate with RTL designers to meet PPA goals and tradeoffs.
• Floor-planning and placement/routing experiments for better PPA.
• Perform timing closure for very high frequency designs; may hand place logic.
• Define low latency/low skew clock tree methodology.
• Define power grid structures to meet EM/IR goals.
• Create regression scripts to run flows on the grid.

Skills

Strong communication

Mentoring juniors

5+ years experience

Verilog knowledge

ASIC design flow

Logic synthesis

Prototyping

Timing analysis

Floor-planning

Flow automation

Innovus experience

Computer architecture

Learning quickly

Milestone delivery

RTL familiarity

PCIe / Ethernet / DDR4 familiarity

Regression scripting

Education

BS or MS Degree in Electrical Engineering or Computer Science

Tools

Innovus

Perl

Tcl

Python

Job description

Tachyum in Las Vegas seeks a senior IC design engineer to drive ultra-high performance, low-power data-processing chips. You will work with RTL teams to meet aggressive PPA targets and contribute to floorplanning, timing closure, and clock-tree design.

The role requires 5+ years in semiconductor design, Verilog expertise, and experience with Innovus. Strong collaboration skills and willingness to mentor junior engineers are essential.