Lead Physical Design Engineer, Advanced Node ICs

Capgemini Engineering; California; In loco; USD 82.000 - 193.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health benefits

Retirement plan

Paid time off

Descrizione del lavoro

Capgemini Engineering in Santa Clara, CA is seeking a seasoned Physical Design Engineer to drive complex digital and mixed-signal IC implementation from floorplanning through tape-out using Cadence Innovus and related tools.

The role requires 10+ years of physical design experience, deep knowledge of the complete PD flow, and expertise in power-grid architectures, STA, and CDC. Together with cross-functional teams, you will push towards optimal performance at 7nm/5nm/3nm nodes.

Competenze

• 10+ years in physical design for digital/mixed-signal ICs.
• Strong knowledge of complete physical design flow.
• Expertise in power-grid, CTS, timing, and signoff.
• Experience with tape-out readiness and foundry signoff.
• Experience with advanced-node designs (7nm/5nm/3nm).

Mansioni

• Lead or support physical design activities: floorplanning, placement, CTS, P&R, and signoff.
• Develop power-grid strategies and high-speed clock constraints.
• Perform physical verification, LVS/DRC debugging at chip/block levels.
• Collaborate with design, layout, verification, timing teams across the lifecycle.
• Support CDC, STA, parasitic-aware simulation and timing closure.
• Contribute to tape-out readiness and foundry interaction.

Conoscenze

Physical design

Full design flow

Power-grid design

STA (Static timing)

CDC analysis

Tape-out readiness

EDA tools Cadence

Strumenti

Cadence Innovus

Quantus

Voltus

Calibre

RedHawk

Descrizione del lavoro

Capgemini Engineering in Santa Clara, CA is seeking a seasoned Physical Design Engineer to drive complex digital and mixed-signal IC implementation from floorplanning through tape-out using Cadence Innovus and related tools.

The role requires 10+ years of physical design experience, deep knowledge of the complete PD flow, and expertise in power-grid architectures, STA, and CDC. Together with cross-functional teams, you will push towards optimal performance at 7nm/5nm/3nm nodes.