Senior Physical Design Engineer - Advanced Node ICs

Capgemini; Santa Clara, Northern (CA, KY); Hybrid; USD 82,000 - 193,000; Full time

Benefits offered by this job

Vacation & Holidays

Personal Days

Sick Leave

Medical Insurance

Dental & Vision

401(k) Retirement

Life & Disability Insurance

Employee Assistance Program

Job summary

Capgemini Engineering in Santa Clara, CA, is seeking a Senior Physical Design Engineer to drive complex IC implementations at advanced nodes. You will lead floorplanning, placement, clock tree synthesis, routing and power-grid strategies, collaborating across teams to meet timing, power and area goals, and ensure tape-out readiness.

The role requires 10+ years in physical design, LVS/DRC debugging, CDC and timing analysis, and hands-on use of Virtuoso, Calibre and similar EDA tools.

Qualifications

• ,

Responsibilities

• Lead or support physical design activities across floorplanning, placement, CTS, routing and physical-aware synthesis.
• Develop and implement robust power-grid strategies and high-speed clock constraints.
• Perform physical verification and debug LVS/DRC issues at chip and block levels.
• Collaborate with design, layout, verification and timing teams to address implementation challenges.
• Support CDC, static timing analysis, parasitic-aware simulation and timing closure.

Skills

10+ years PD experience

Floor planning

Place & Route

Clock tree synthesis

Power-grid strategies

LVS/DRC debugging

CDC & timing analysis

EDA tools expertise

Tools

Virtuoso

Calibre

RedHawk

Job description

Capgemini Engineering in Santa Clara, CA, is seeking a Senior Physical Design Engineer to drive complex IC implementations at advanced nodes. You will lead floorplanning, placement, clock tree synthesis, routing and power-grid strategies, collaborating across teams to meet timing, power and area goals, and ensure tape-out readiness.

The role requires 10+ years in physical design, LVS/DRC debugging, CDC and timing analysis, and hands-on use of Virtuoso, Calibre and similar EDA tools.