Senior Physical Design Engineer – Advanced-Node IC

Capgemini Engineering; California (MO); On-site; USD 82,000 - 193,000; Full time

Benefits offered by this job

Medical coverage

Dental coverage

Vision coverage

401(k)

Job summary

Capgemini Engineering is seeking a senior Physical Design Engineer in a on-site Santa Clara location to drive complex digital/mixed-signal IC implementation from floorplanning through tape-out.

You will lead design activities, optimize power-grid strategies, perform LVS/DRC checks, and collaborate with cross-functional teams to meet PPA goals for 3nm–7nm nodes. Strong ADM/EDA tool expertise is required.

Qualifications

• 10+ years of Physical Design experience
• Complete physical design flow including floorplanning, placement, CTS, P&R, and timing closure
• Power-grid architectures and high-speed clock constraints
• STA with timing closure across multiple corners
• CDC analysis and timing signoff
• Physical verification and signoff (DRC/LVS)
• Interaction of digital and analog/layout requirements
• Tape-out readiness and foundry signoff for advanced nodes
• PPA tradeoffs in advanced-node implementations
• TSMC 7nm/5nm/3nm or below experience

Responsibilities

• Lead or support physical design activities: floorplanning, placement, CTS, routing, and physical-aware synthesis
• Develop and implement power-grid strategies and high-speed clock constraints
• Perform LVS/DRC debugging at chip and block levels
• Collaborate across design, layout, verification, timing, and methodology teams
• Support CDC, STA analyses, parasitic-aware simulations, and timing closure
• Contribute to tape-out readiness with design signoff and foundry coordination
• Evaluate tradeoffs in power, area, performance, and technology limits for advanced nodes

Skills

Physical Design

CTS

P&R (Place-and-Route)

STA

CDC Analysis

LVS/DRC

Tape-out readiness

Power integrity

Advanced-node tech

Foundry signoff

Tools

Cadence Innovus

Quantus

Voltus

Calibre

RedHawk

Job description

Capgemini Engineering is seeking a senior Physical Design Engineer in a on-site Santa Clara location to drive complex digital/mixed-signal IC implementation from floorplanning through tape-out.

You will lead design activities, optimize power-grid strategies, perform LVS/DRC checks, and collaborate with cross-functional teams to meet PPA goals for 3nm–7nm nodes. Strong ADM/EDA tool expertise is required.