Senior Physical Design Engineer - 7nm Tapeouts

Voltai; United States; Sur place; USD 140 000 - 200 000; Plein temps

Résumé du poste

Voltai is building world-class physical design teams to take designs from netlist to GDSII and deliver silicon-ready flows. You will own block-level and full-chip implementation, drive timing and power closure, and collaborate with AI-enabled design improvements.

You’ll work with Innovus or Fusion Compiler on 7nm and below nodes, write Tcl/Python scripts to automate flows, and directly partner with customer teams to solve challenging implementation problems.

Qualifications

• 5+ years of physical design experience with multiple production tapeouts.
• Deep experience with Innovus or Fusion Compiler/ICC2.
• Strong understanding of timing closure, clock tree synthesis, and power distribution networks.
• Experience at advanced nodes (7nm and below).
• Strong Tcl and Python scripting.

Responsabilités

• Own block-level and full-chip physical implementation: floorplanning, placement, clock tree synthesis, and routing.
• Drive timing, power, and congestion closure with synthesis and STA teams.
• Close physical verification (DRC/LVS) and power integrity (IR drop, EM) for signoff.
• Build and improve place-and-route flows and automation.
• Evaluate AI-generated floorplans and implementation decisions, and help define what good looks like.
• Work directly with customer teams on implementation challenges.

Connaissances

Physical design

Tcl scripting

Python scripting

Timing closure

Outils

Innovus

ICC2 / Fusion Compiler

Fusion Compiler

Description du poste

Voltai is building world-class physical design teams to take designs from netlist to GDSII and deliver silicon-ready flows. You will own block-level and full-chip implementation, drive timing and power closure, and collaborate with AI-enabled design improvements.

You’ll work with Innovus or Fusion Compiler on 7nm and below nodes, write Tcl/Python scripts to automate flows, and directly partner with customer teams to solve challenging implementation problems.