Physical Design Engineer: AI-Driven 7nm Chip Implementation

Voltai; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Voltai is building world models and agents to learn, evaluate, plan, and interact with the physical world. You will own block-level and full-chip physical implementation, guiding floorplanning, placement, clock tree synthesis, routing, and verification on silicon programs with leading semiconductor partners.

You will drive timing closure, power integrity, and congestion control in collaboration with synthesis and STA teams, while evaluating AI-generated floorplans and decisions.

Qualifications

• 5+ years of physical design experience with multiple production tapeouts.
• Strong background in timing closure, clock tree synthesis, and power distribution networks.
• Experience with advanced nodes (7nm and below) is preferred.

Responsibilities

• Own block-level and full-chip physical implementation: floorplanning, placement, CTS, routing.
• Drive timing, power, and congestion closure with synthesis and STA teams.
• Close physical verification (DRC/LVS) and power integrity checks for signoff.
• Build and improve place-and-route flows and automation.
• Evaluate AI-generated floorplans and implementation decisions, and define what good looks like.
• Work directly with customer teams on implementation challenges.

Skills

Physical design

Timing closure

Floorplanning

Power integrity

Tools

Innovus

ICC2

Python scripting

Tcl scripting

Job description

Voltai is building world models and agents to learn, evaluate, plan, and interact with the physical world. You will own block-level and full-chip physical implementation, guiding floorplanning, placement, clock tree synthesis, routing, and verification on silicon programs with leading semiconductor partners.

You will drive timing closure, power integrity, and congestion control in collaboration with synthesis and STA teams, while evaluating AI-generated floorplans and decisions.