Senior Physical Design AI/ML Engineer | PPA Optimization

Engg; San Jose (CA); On-site; USD 190,000 - 240,000; Full time

Benefits offered by this job

4+ weeks PTO

Holidays & sick leave

Fertility/adoption stipend

Medical/Dental/Vision/401k

Job summary

Samsung Semiconductor Inc (SSI) in San Jose seeks a Senior Physical Design AI/ML Engineer to advance DTCO and sub-2nm design strategies. You will combine ML with EDA flows to optimize PPA, collaborate across teams, and drive technology transfer to Korea.

Responsibilities include researching device architectures, libraries, and device integration concepts while leading design-rule checks and PDK exploration with strong communication across organizations.

Qualifications

• PhD with industry experience preferred.
• RTL synthesis, place & route, and timing analysis required.
• Strong Python and C++ with ML libraries.

Responsibilities

• Design machine learning models to optimize chip layouts for PPA efficiency.
• Automate floorplanning, placement and routing, and clock tree synthesis.
• Automate DRC and LVS checks using exploratory PDKs.
• Collaborate to generate automated QA for PDKs.
• Explore data correlations across device and circuit blocks.
• Develop benchmarking methods and share with R&D teams.
• Perform other duties as assigned.

Skills

Python

C++

ML/AI

RTL synthesis

Place & Route

Timing analysis

Bayesian optimization

Graph nets

Communication

Education

PhD

Tools

LangGraph

CrewAI

ADK

PyTorch

TensorFlow

Job description

Samsung Semiconductor Inc (SSI) in San Jose seeks a Senior Physical Design AI/ML Engineer to advance DTCO and sub-2nm design strategies. You will combine ML with EDA flows to optimize PPA, collaborate across teams, and drive technology transfer to Korea.

Responsibilities include researching device architectures, libraries, and device integration concepts while leading design-rule checks and PDK exploration with strong communication across organizations.