Senior Engineer, Physical Design AI/ML

Engg; San Jose (CA); On-site; USD 190,000 - 240,000; Full time

Benefits offered by this job

4+ weeks PTO

Holidays & sick leave

Fertility/adoption stipend

Medical/Dental/Vision/401k

Job summary

Samsung Semiconductor Inc (SSI) in San Jose seeks a Senior Physical Design AI/ML Engineer to advance DTCO and sub-2nm design strategies. You will combine ML with EDA flows to optimize PPA, collaborate across teams, and drive technology transfer to Korea.

Responsibilities include researching device architectures, libraries, and device integration concepts while leading design-rule checks and PDK exploration with strong communication across organizations.

Qualifications

• PhD with industry experience preferred.
• RTL synthesis, place & route, and timing analysis required.
• Strong Python and C++ with ML libraries.

Responsibilities

• Design machine learning models to optimize chip layouts for PPA efficiency.
• Automate floorplanning, placement and routing, and clock tree synthesis.
• Automate DRC and LVS checks using exploratory PDKs.
• Collaborate to generate automated QA for PDKs.
• Explore data correlations across device and circuit blocks.
• Develop benchmarking methods and share with R&D teams.
• Perform other duties as assigned.

Skills

Python

C++

ML/AI

RTL synthesis

Place & Route

Timing analysis

Bayesian optimization

Graph nets

Communication

Education

PhD

Tools

LangGraph

CrewAI

ADK

PyTorch

TensorFlow

Job description

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Job Title Senior Physical Design AI/ML Engineer, Logic Pathfinding Lab

What You’ll Do

We are looking for physical design engineers who have demonstrated skills in applying AI / Machine Learning tools in improving design simulation accuracy and throughput in predicting design performance, power, and area (PPA).

Experience in optimization of design-technology co-optimization (DTCO) knobs in advanced logic nodes (2nm or beyond) is preferred. The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose. He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea.

The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes. The candidate should have demonstrated skills and experience in standard cell architecture creation, logic cell library characterizations Place and Route, Process Design Kit (PDK) generation, and a strong understanding of Logic process integration. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.

Location: Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy Reports to: Sr Director Direct Reports: N/A

• Design, build, and implement machine learning and generative models to optimize chip layout designs to maximize performance, power, and area (PPA) efficiency, while using explicit domain knowledge of hardware design rules and constraints
• Automate and accelerate Design Implementation steps such as Floor-planning, Placement and Routing, Clock Tree Synthesis, using exploratory PDKs developed by the team
• Automate and accelerate Verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) Checks using exploratory PDKs developed by the team
• Collaborate with other team members to automate all aspects of exploratory PDK generation, including developing automated QA systems
• Applying machine learning techniques to extract and develop correlations among data in different domains, e.g. device, RO benchmark circuits, larger circuit blocks, at different operating conditions
• Develop internal benchmarking capability based on available data, modeling, or learning from multiple sources, and create assessments to share with internal R&D team
• Complete other responsibilities as assigned.

What You Bring

• PhD with industry experience preferred
• RTL synthesis, place and route, and timing analysis skills
• Understanding of clock and power delivery network schemes
• Hands‑on experience on machine learning or deep learning projects for scientific and/or engineering applications, e.g., regression, surrogate modeling, inverse design, graph neural networks
• Strong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and Tensorflow
• Experience in using Bayesian optimization and/or active learning frameworks for design space exploration
• Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK)
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Preferred qualifications

• Familiarity with state-of-the-art AI workloads and their compute and memory requirements
• Experience with setting up and optimization of a local, private, compute cluster to run latest LLM models
• Proficiency in EDA tools for synthesis and layout
• Prior experience using generative AI for chip design/optimization #LI-SF1

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

• Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
• Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
• Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
• Prioritize Emotional Wellness With on-demand apps and free confidentia