Senior AI/ML Physical Design Engineer

Conductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks paid time off

Healthcare benefits

Onsite café & gym

Flexible work policy

Job summary

Samsung Semiconductor, Inc. in San Jose, CA, seeks a Senior Physical Design AI/ML Engineer to advance DTCO and sub-2nm exploration. You will join the Logic Pathfinding Lab and collaborate across research and TD teams to evaluate new device architectures and implement ML-driven design flows.

The role requires strong ML/AI skills, RTL, place-and-route, timing analysis, and hands-on hardware design knowledge, with onsite daily presence per policy.

Qualifications

• PhD with industry experience preferred
• RTL synthesis, place and route, and timing analysis skills
• Understanding of clock and power delivery network schemes
• Hands-on experience on machine learning projects for scientific/engineering applications
• Strong Python and/or C++ skills, including ML packages like PyTorch and TensorFlow
• Experience with Bayesian optimization/active learning for design space exploration
• Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK)
• Collaborative and adaptable to diverse global norms

Responsibilities

• Design, build, and implement ML models to optimize chip layout for PPA efficiency
• Automate floorplanning, placement and routing, clock tree synthesis
• Automate DRC and LVS verification
• Collaborate to automate exploratory PDK generation and QA systems
• Apply ML to extract correlations across device/benchmarks/conditions
• Develop internal benchmarking using data/modeling/multi-source learning
• Complete other responsibilities as assigned

Skills

Python

C++

Machine learning

RTL synthesis

Place and Route

Timing analysis

PPA optimization

AI frameworks

Education

PhD

Tools

PyTorch

TensorFlow

EDA tools

Job description

Samsung Semiconductor, Inc. in San Jose, CA, seeks a Senior Physical Design AI/ML Engineer to advance DTCO and sub-2nm exploration. You will join the Logic Pathfinding Lab and collaborate across research and TD teams to evaluate new device architectures and implement ML-driven design flows.

The role requires strong ML/AI skills, RTL, place-and-route, timing analysis, and hands-on hardware design knowledge, with onsite daily presence per policy.