Senior AI/ML Engineer for Chip Layout Optimization

Samsungsemiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Diversity & Benefits

Flexible work policy

Job summary

Samsung Semiconductor Inc in San Jose seeks a Senior Physical Design AI/ML Engineer for the Logic Pathfinding Lab. You will apply AI/ML to improve design simulation accuracy and throughput, and contribute to DTCO knob optimization for sub-2nm nodes.

The role requires a PhD with hands-on RTL synthesis, place & route, PDK generation, and collaboration across teams. Strong Python/C++ and ML frameworks are essential, with onsite presence in San Jose.

Qualifications

• PhD with industry experience preferred.
• RTL synthesis, place and route, and timing analysis skills.
• Understanding of clock and power delivery network schemes.
• Hands-on experience on ML/DL projects for scientific/engineering applications (regression, surrogate modeling, inverse design, GNNs).

Responsibilities

• Design, build, and implement ML/gen models to optimize chip layouts for PPA efficiency.
• Automate Floorplanning, Placement and Routing, Clock Tree Synthesis.
• Automate DRC and LVS checks with exploratory PDKs.
• Collaborate to automate exploratory PDK generation and QA systems.
• Apply ML to extract correlations among data across domains (device, RO benchmarks, blocks).
• Develop benchmarking capability from available data and share assessments with R&D.

Skills

Python

C++

Machine Learning

PyTorch

TensorFlow

Bayesian optimization

Active learning

RTL synthesis

Place and route

Timing analysis

Communication

Education

PhD

Tools

EDA tools

Synthesis tools

Layout tools

Job description

Samsung Semiconductor Inc in San Jose seeks a Senior Physical Design AI/ML Engineer for the Logic Pathfinding Lab. You will apply AI/ML to improve design simulation accuracy and throughput, and contribute to DTCO knob optimization for sub-2nm nodes.

The role requires a PhD with hands-on RTL synthesis, place & route, PDK generation, and collaboration across teams. Strong Python/C++ and ML frameworks are essential, with onsite presence in San Jose.