Senior Staff ASIC Physical Design Engineer (On-Site)

Bolt Graphics; Sunnyvale (CA); Sur place; USD 200 000 - 220 000; Plein temps

Avantages offerts par ce poste

Medical, Dental & Vision premiums 100%

Equity - Stock Options

401(k) match

Résumé du poste

Bolt Graphics in Sunnyvale, CA, is seeking a Staff / Senior Staff Physical Design Engineer to drive full-chip physical implementation from netlist to GDSII, targeting timing, power, and area targets for high-performance graphics processors.

This on-site role requires 5 days in the office, with ownership of flow, timing closure, signoff, and cross-functional collaboration with RTL, architecture, and foundry teams.

Qualifications

• Bachelor's/Master's degree in Electrical Engineering or related field.
• 8-12 years of ASIC physical design experience.
• Proven experience in full-chip or large block implementation and tapeouts.
• Strong expertise in floorplanning and power planning.
• Placement, CTS, routing, and physical verification.
• Static Timing Analysis (STA) and timing closure.
• Hands-on with industry-standard tools such as Synopsys ICC2 and Cadence Innovus.
• Experience with advanced nodes (7nm and below preferred).
• Strong debugging and problem-solving skills.

Responsabilités

• Own end-to-end physical design flow: synthesis support, floorplanning, placement, CTS, routing, signoff.
• Drive timing closure across multiple PVT corners using STA methodologies.
• Perform and debug DRC/LVS/EM/IR issues and drive clean signoff.
• Collaborate with RTL, architecture, and verification teams for design convergence.
• Handle ECO flows, including late-stage timing and functional fixes.
• Optimize designs for power, performance, and area (PPA).
• Integrate and validate hard macros (SRAMs, IOs, analog blocks).
• Develop automation scripts (TCL/Python) for PD flows.
• Collaborate with foundry/vendor teams during tapeout and signoff.

Connaissances

Floorplanning

Power planning

Placement

CTS

Routing

SDA/STA

Signoff

Python/TCL scripting

Debugging

Formation

Bachelor's/Master's in Electrical Engineering

Outils

Synopsys ICC2

Cadence Innovus

Advanced node knowledge (7nm)

Description du poste

Bolt Graphics in Sunnyvale, CA, is seeking a Staff / Senior Staff Physical Design Engineer to drive full-chip physical implementation from netlist to GDSII, targeting timing, power, and area targets for high-performance graphics processors.

This on-site role requires 5 days in the office, with ownership of flow, timing closure, signoff, and cross-functional collaboration with RTL, architecture, and foundry teams.