Senior SoC Power Engineer for AI Accelerators

Annapurna Labs; Cupertino (CA); On-site; USD 213,000 - 288,000; Full time

Benefits offered by this job

Health insurance

RSUs

Paid time off

Job summary

Annapurna Labs (U.S.) Inc. is seeking a Sr. SoC Power Engineer to model and estimate chip power from RTL to netlist, and drive power reduction across the MLA SoC designs powering Inf nerentia/Trainium accelerators.

You will work with architects, designers, verification, software, and Physical Design teams to implement best practices for power efficiency. Based in Cupertino, CA, you will develop power dashboards, analyze IR/thermal data, and drive lab power measurement programs to ensure accuracy

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or related fields.
• BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS
• Expert on power analysis tools like PrimePower, PowerArtist or similar
• Deep, circuit-level understanding of chip power
• Ability to give feedback to RTL designers and Physical Designers on how to reduce power
• Highly proficient with scripting language (Tcl, Perl, Python or similar)
• Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level
• Some experience with lab equipment and capable of doing lab power analysis

Responsibilities

• Perform full chip power analysis and modelling from RTL to gate-level netlist.
• Develop and maintain dashboards for power rollups.
• Create IR, thermal, and power analysis vectors with designers and PD.
• Provide feedback to designers and architects on power reduction.
• Make power measurements in lab and correlate with simulations.
• Collaborate with Emulation engineers to model chip power consumption

Skills

Power analysis

Scripting

RTL feedback

Lab measurements

Power integrity

Education

Bachelor's degree in EE/CS

Master's degree in EE/CS

PhD in EE/CS

Tools

PrimePower

PowerArtist

Redhawk

Voltus

Zebu Emulator

Job description

Annapurna Labs (U.S.) Inc. is seeking a Sr. SoC Power Engineer to model and estimate chip power from RTL to netlist, and drive power reduction across the MLA SoC designs powering Inf nerentia/Trainium accelerators.

You will work with architects, designers, verification, software, and Physical Design teams to implement best practices for power efficiency. Based in Cupertino, CA, you will develop power dashboards, analyze IR/thermal data, and drive lab power measurement programs to ensure accuracy