Senior Design Verification Engineer – PCIe Subsystem (PCIe Gen6)

ALTEN; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

ALTEN in San Jose, CA seeks an experienced verification engineer to verify CPU subsystems and SoC interfaces using SystemVerilog/UVM. You will develop testbenches, plans, assertions, and functional coverage while collaborating with Architecture and RTL teams.

The role requires strong scripting skills (Python/Perl/Shell) and hands-on experience with verification IP integration, AXI/AMBA interfaces, and regression cycles. On-site position in Silicon Valley with potential for long-term impact.

Qualifications

• 5–12+ years of CPU/SoC verification experience.
• Strong SystemVerilog/UVM expertise for testbench development.
• Experience with AXI/AMBA interfaces and verification IP integration.
• Proficiency with scripting (Python/Perl/Shell) for automation.

Responsibilities

• Verify CPU subsystem and standard interfaces using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and coverage.
• Verify CPU functionality, interconnects, interrupts, coherency, power management.
• Execute regressions, debug RTL/design issues, and drive coverage closure.
• Collaborate with Architecture, RTL, and Validation for verification signoff.

Skills

CPU verification experience

SystemVerilog/UVM

Automation scripting

Tools

AXI/AMBA interfaces

Verification IP integration

Xcelium/VCS/Questa

Job description

Experience: 5–12+ Years

Responsibilities

• Verify CPU subsystem and standard interfaces using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify CPU subsystem functionality, interconnects, interrupts, coherency, power management, and exception handling.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Required Skills

• Strong SystemVerilog/UVM expertise.
• Experience verifying CPU subsystems or SoC integration.
• Good understanding of AXI/AHB/APB and standard SoC interfaces.
• Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
• Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).