Principal Engineer, PCIe Verification (AI2441)

SiMa.ai; San Jose (CA); On-site; USD 220,000 - 296,400; Full time

Benefits offered by this job

Equity

Job summary

SiMa.ai in San Jose, CA is seeking a Principal Engineer for PCIe Verification to lead formal verification efforts for PCIe controllers and PHYs across block, sub‑system, and MLSoC levels.

You will drive PCIe bring‑up, debug on emulation, and work on UCIe interface verification on next‑gen projects, collaborating with architectures and MLSoC teams. The role requires deep SV/UVM experience and strong programming skills.

Qualifications

• BS/MS in Electrical Engineering or Computer Science with 12+ years of experience in functional verification and silicon bring‑up/debug.
• Strong experience with UVM and SystemVerilog based verification methodologies.
• Experience with PCIe Gen4/5 and PCIe bring‑up on silicon is a plus.
• Proficiency in C/C++/Python programming is a plus.

Responsibilities

• Participate in PCIe architecture discussions and reviews.
• Define and develop PCIe test bench components using UVM & SystemVerilog.
• Bring up and test PCIe in block and full‑chip environments.
• Develop and execute a test plan for PCIe verification.
• Verify PCIe EP/RC functionality and measure performance.
• Lead code coverage reviews and closure; SystemVerilog assertion coverage.

Skills

UVM

SystemVerilog

C/C++/Python

Education

Bachelor/Master in Electrical Engineering or Computer Science

Job description

Principal Engineer, PCIe Verification – San Jose, CA

The Design Verification (DV) engineer at SiMa is involved in the functional verification of PCIe controller and PCIe‑phy at block, sub‑system and MLSoC levels. Will also be involved in PCIe bring‑up and debug on emulator. Generate required PCIe controller and phy initialization (register programming code sequence) for PCIe bring up in Simulation, emulation and on silicon. Work on UCIe interface verification on next generation projects.

Responsibilities

• Participate in PCIe architecture, micro‑architecture, feature discussions and reviews.
• Define and develop PCIe test bench components using UVM & System Verilog.
• Bring up and testing of PCIe in block and full‑chip test environment.
• Develop and execute a test plan.
• Verification execution of PCIe EP/RC functionality and performance measurements.
• Lead code coverage reviews and closure. SystemVerilog assertion functional coverage development and closure.
• Manage debug of test and regression failures, as well as emulation failures.
• Work closely with the Architecture, MLSoC Hardware and MLA Software teams.
• Work with emulation and MLSoC Software team to bring up and debug PCIe.
• Work in the lab on PCIe interface silicon debug with software and systems team as needed.

Qualifications

• BS/MS in Electrical Engineering or Computer Science with 12+ years of experience in functional verification and silicon bring‑up/debug.
• Very good current working experience of UVM and System Verilog based verification methodology is a must.
• Working experience on PCIe protocols Gen4/5.
• Working experience on PCIe bring‑up and debug on Silicon is a plus.
• Past working experience on UCIe protocols is a plus.
• Proficiency in C/C++/Python programming is a plus.
• Good debug and problem solving skill.

Personal Attributes

Can‑do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results‑oriented. Self‑driven, thinks big and is highly accountable. Good communication skills.

Salary & Benefits

The annual salary for this position ranges from $220,000 - $296,400. The actual annual salary offered will depend on several factors, including job‑related skills, experience, technical expertise, qualifications, work location, and business needs. A private company equity, and a comprehensive package of employee benefits may also be included. Base salary references are U.S. only.

EEO Statement

SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.