Senior PCB Layout Engineer for AI Compute Hardware

MatX; Mountain View (CA); On-site; USD 160,000 - 600,000; Full time

Benefits offered by this job

4 weeks PTO + holidays

Remote work up to 3 weeks

Medical insurance

401K with company contribution

Professional development budget

Team meals

Commute covered

Life insurance

Home office stipend

Job summary

MatX is building next-generation AI compute infrastructure. They seek an experienced PCB Layout Engineer to design high-density boards for AI chip, compute trays, and rack-scale platforms in Mountain View, CA.

You will own layouts from floorplanning to Gerber release, ensuring signal and power integrity and working with JDM/ODM partners on complex multi-layer boards and high-speed interfaces.

Qualifications

• 7+ years of PCB layout experience on multi-layer boards (20+ layers) for AI compute or high-performance hardware.
• Proficiency in Cadence Allegro or equivalent EDA tool with deep high-speed design expertise.
• Hands-on experience with fine-pitch BGA, high-density packages, and high-speed interfaces (PCIe Gen5/6, CXL, 112G/224G SerDes).

Responsibilities

• Own PCB layout from floorplanning to Gerber release for complex boards.
• Design high-speed differential routing with impedance control and length matching.
• Plan stack-ups and place/route complex BGAs, including AI ASICs.
• Design PDN, VRM placement, decoupling, and power planes; collaborate on simulations.
• Coordinate with mechanical on board outline and chassis constraints.
• Lead design, layout, and DFM reviews with partners and manage release packages.

Skills

High-speed PCB design

Differential routing

Impedance control

Length matching

PCIe Gen5/6, CXL

BGA placement/routing

SI/PI interpretation

Tools

Cadence Allegro

Ansys SIwave

Cadence Sigrity

Job description

MatX is building next-generation AI compute infrastructure. They seek an experienced PCB Layout Engineer to design high-density boards for AI chip, compute trays, and rack-scale platforms in Mountain View, CA.

You will own layouts from floorplanning to Gerber release, ensuring signal and power integrity and working with JDM/ODM partners on complex multi-layer boards and high-speed interfaces.