Lead High-Speed PCB Designer for AI Accelerator Cards

d-Matrix; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

d-Matrix in Santa Clara, CA is seeking a Sr. Staff PCB Design Engineer to lead the physical design of AI accelerator boards that connect our silicon to the world.

You will own layouts for 20+ layer boards, ensure 112G/224G SerDes integrity, and drive automation and constraint management with cross-functional teams. You will partner with power, ASIC, and manufacturing teams to build scalable layout infrastructure, while delivering high-yield production through DFM and DFA cooperation.

Qualifications

• BS in Electrical/Electronic Engineering or equivalent.
• 10+ years in high-speed PCB layout for servers, networking, or AI accelerators.
• Proficiency with Cadence Allegro Constraint Manager and related features.
• Ability to write and deploy SKILL scripts or automate design checks.
• Deep knowledge of high-speed routing techniques and HDI design.

Responsibilities

• Lead full-cycle layout for high-complexity AI accelerator cards and system baseboards.
• Architect and manage the Constraint Manager hierarchy for high-speed routing rules.
• Develop automation scripts to streamline layout tasks, DRC checks, and reporting.
• Execute layout for PCIe Gen5/6, CXL, and die-to-die interconnects.
• Collaborate with Power, ASIC, and manufacturing teams to scale hardware dev.
• Drive PCB stack-up definition with advanced materials and multi-layer builds.
• Interface with fabricators to ensure DFM/DFT/DFX for high-yield production.

Skills

Electrical engineering

10+ years experience

Cadence Allegro CM

SKILL scripting

High-speed routing

112G SerDes routing

Education

BS in Electrical/Electronic Engineering

Tools

Cadence Allegro

Allegro API

Job description

d-Matrix in Santa Clara, CA is seeking a Sr. Staff PCB Design Engineer to lead the physical design of AI accelerator boards that connect our silicon to the world.

You will own layouts for 20+ layer boards, ensure 112G/224G SerDes integrity, and drive automation and constraint management with cross-functional teams. You will partner with power, ASIC, and manufacturing teams to build scalable layout infrastructure, while delivering high-yield production through DFM and DFA cooperation.