Senior Package Layout Engineer | Hybrid + Equity Options

NVIDIA; Santa Clara (CA); Hybrid; USD 136,000 - 259,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara is seeking a Senior Package Layout Engineer to design high-speed ASIC packages and collaborate with fast-moving design teams.

You will optimize substrate layouts, develop CAD libraries, and drive productivity using Cadence APD, SiP tools, and related workflows. The role focuses on performance, size, cost trade-offs, and close alignment with package and system goals, with Hybrid work options.

Qualifications

• Hold a B.S. Electrical Engineering or equivalent experience.
• 5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology.
• Proven experience in substrate layout of wire bond and flip chip packages.
• Significant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager).
• Solid understanding of high-speed design signal integrity practices.
• Experience with Virtuoso and Calibre is a plus.
• Experience using Valor is helpful.

Responsibilities

• Collaborate to implement high speed/density ASIC packages.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pinout incorporating system level trade-offs of pins assignment.
• Assist in package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.
• Propose layout design trade-offs to the Technical Package Lead for resolution and implementation.
• Conduct design feasibility studies to evaluate size, cost, and system performance goals.
• Develop symbols and CAD library databases using Cadence APD design tools.
• Develop methodologies to improve layout productivity.

Skills

PCB Layout

HDI designs

Substrate layout

Signal integrity

Education

B.S. Electrical Engineering or equivalent experience

Tools

Cadence APD

SiP tool suite

Constraint Manager

Virtuoso

Calibre

Valor

Job description

NVIDIA in Santa Clara is seeking a Senior Package Layout Engineer to design high-speed ASIC packages and collaborate with fast-moving design teams.

You will optimize substrate layouts, develop CAD libraries, and drive productivity using Cadence APD, SiP tools, and related workflows. The role focuses on performance, size, cost trade-offs, and close alignment with package and system goals, with Hybrid work options.