Senior NVLink I/O Architect — Chip-to-Chip Interconnects

NVIDIA Corporation; Santa Clara (CA); Sur place; USD 224 000 - 431 000; Plein temps

Avantages offerts par ce poste

Equity

Benefits

Résumé du poste

NVIDIA is seeking a Senior I/O Architect for its NVLink chip-to-chip team in Santa Clara, CA. You will lead architecture efforts for high-performance interconnects, model and document interfaces, and drive implementation across design, verification, firmware, and software teams.

The role requires advanced degrees and 10+ years in related fields, with deep experience in link-layer architectures and industry protocols.

Qualifications

• MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience).
• 10+ years of relevant experience in architecture, design, and verification.
• Proven experience over link layer architecture (Transaction, Data link, Physical).
• Experience with interconnects and CHI/CXL/AXI protocols.
• Define system architecture with NVLINK-C2C interconnects and SW stack.
• Collaborate with IP, SoC, physical/package design, firmware, electrical design and validation.
• Evaluate and trade off technical solutions to meet platform requirements.
• Led multiple projects from concept through product lifecycle including prototyping and deployment.

Responsabilités

• Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
• Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip
• Architectural modeling, validation, definition and documentation
• Driving implementation across design, verification, firmware and software teams
• Working with various teams to define NVLink C2C architecture

Connaissances

IO architecture

Technical leadership

Interconnect protocols

NVLink C2C

Formation

MS or PhD in Electrical Eng./CS/CE

Outils

PCIe

CHI/CXL/AXI

Description du poste

NVIDIA is seeking a Senior I/O Architect for its NVLink chip-to-chip team in Santa Clara, CA. You will lead architecture efforts for high-performance interconnects, model and document interfaces, and drive implementation across design, verification, firmware, and software teams.

The role requires advanced degrees and 10+ years in related fields, with deep experience in link-layer architectures and industry protocols.