Senior Low-Power HSIO Architect – NVLink & Interconnects

NVIDIA; Arizona; On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join the HW ArchDev team, with end-to-end involvement from arch definition through bringup to product release. You will work on next-gen HSIO, including NVLink and NVLink-C2C, focusing on energy efficiency and system-level integration.

The role requires deep HSIO experience, ownership across multiple teams, and strong fundamentals in power analysis, timing, and architecture.

Qualifications

• BS or MS degree in EE/CE or equivalent experience.
• 10+ years working on HSIO with power management, modeling, bringup or debugging.
• Experience with system-level power optimization and firmware/driver interactions.

Responsibilities

• Design next-gen high-speed IOs like NVLink and NVLink-C2C.
• Optimize IO power and energy efficiency.
• Ensure interoperability within complex interconnect topologies.
• Debug HSIO issues across multiple teams.
• Collaborate with system architects, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive design, development, debug, and release of next-generation products.

Skills

HSIO fundamentals

Power management

High-speed interfaces

Power / perf modeling

System integration

Education

Bachelor's or Master's in EE/CE

Job description

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join the HW ArchDev team, with end-to-end involvement from arch definition through bringup to product release. You will work on next-gen HSIO, including NVLink and NVLink-C2C, focusing on energy efficiency and system-level integration.

The role requires deep HSIO experience, ownership across multiple teams, and strong fundamentals in power analysis, timing, and architecture.