Low-Power GPU/SOC Feature Architect (NVLink)

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join the HW ArchDev team, working on next-gen high-speed interconnects like NVLink and NVLink-C2C. You will contribute to IO power optimizations and ensure interoperability across complex interconnect topologies.

This role involves deep debugging, collaboration with system architects, firmware and software teams, and bringing up silicon from arch definition through release.

Qualifications

• BS or MS degree in EE/CE or equivalent experience.
• Minimum 10 years working on capacity - power management, use case analysis, perf/power modeling, bringup, and/or debug.
• Experience with system-level and interconnect power management optimizations.
• Silicon and platform-level power modeling for active/idle use cases.
• Understanding of firmware/driver structures and their interaction with HW.
• Track record of influence, leadership, and collaboration across multiple teams.
• Strong EE fundamentals, knowledgeable in computer architecture and high-speed interfaces.

Responsibilities

• Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C.
• Responsible for IO power optimizations and continuing to push energy efficiency.
• Ensure interoperability with connected devices and system components in complex interconnect topologies
• Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams
• Work closely with system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive design, development, debug, and release of next-generation products.

Skills

Power management

System-level design

High-speed IOs

NVLink NVLink-C2C

Firmware interaction

Cross-team leadership

Timing analysis

Power modeling

Debugging

HW/SW collaboration

Education

BS or MS in EE/CE or equivalent

Job description

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join the HW ArchDev team, working on next-gen high-speed interconnects like NVLink and NVLink-C2C. You will contribute to IO power optimizations and ensure interoperability across complex interconnect topologies.

This role involves deep debugging, collaboration with system architects, firmware and software teams, and bringing up silicon from arch definition through release.