Senior Low-Power HSIO & NVLink Architect

NVIDIA; Austin (TX); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join the HW ArchDev team in Austin. You will work on next-generation high-speed IOs like NVLink and NVLink-C2C, focusing on power optimization and energy efficiency across interconnect topologies.

Senior level responsibilities include leading cross-team initiatives, debugging HSIO issues, and collaborating with architects, DGX, firmware, and QA teams to bring next-generation products to release.

Qualifications

• BS or MS degree in EE/CE or equivalent experience.
• 10+ years working on HSIO with power management, perf/power modeling, bringup, and/or debug.
• Experience with system-level and interconnect power management optimizations.
• Silicon and platform-level power modeling for active/idle use cases.
• Understanding of firmware/driver structures and their interaction with HW.
• Track record of influence, leadership, and collaboration across multiple teams toward a unified goal.
• Strong EE fundamentals, knowledgeable in computer architecture, high-speed interfaces, timing analysis, process variations, statistical error rates, and power analysis.

Responsibilities

• Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C.
• Responsible for IO power optimizations and continuing to push energy efficiency.
• Ensure interoperability with connected devices and system components in complex interconnect topologies
• Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams
• Work closely and proactively with other engineering teams such as system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive design, development, debug, and release of next-generation products.

Skills

HSIO experience

Power management

Power modeling

Bring-up

Debug

Firmware/driver basics

Leadership

Collaboration

Education

BS/MS in EE/CE

Job description

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join the HW ArchDev team in Austin. You will work on next-generation high-speed IOs like NVLink and NVLink-C2C, focusing on power optimization and energy efficiency across interconnect topologies.

Senior level responsibilities include leading cross-team initiatives, debugging HSIO issues, and collaborating with architects, DGX, firmware, and QA teams to bring next-generation products to release.